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june 2009 i ? 2009 actel corporation see the actel website for the latest version of the datasheet. v5.8 proasic plus ? flash family fpgas features and benefits high capacity commercial and industrial ? 75,000 to 1 million system gates ? 27 k to 198 kbits of two-port sram ? 66 to 712 user i/os military ? 300, 000 to 1 million system gates ? 72 k to 198 kbits of two port sram ? 158 to 712 user i/os reprogrammable fl ash technology ? 0.22 m 4 lm flash-based cmos process ? live at power-up (lapu) level 0 support ? single-chip solution ? no configuration device required ? retains programmed design during power-down/up cycles ? mil/aero devices operate over full military temperature range performance ? 3.3 v, 32-bit pci, up to 50 mhz (33 mhz over military temperature) ? two integrated plls ? external system performance up to 150 mhz secure programming ? the industry?s most effective security key (flashlock ? ) low power ? low impedance flash switches ? segmented hierarchical routing structure ? small, efficient, configurable (combinatorial or sequential) logic cells high performance routing hierarchy ? ultra-fast local and long-line network ? high-speed very long-line network ? high-performance, low skew, splittable global network ? 100% routability and utilization i/o ? schmitt-trigger option on every input ? 2.5 v/3.3 v support with indivi dually-selectable voltage and slew rate ? bidirectional global i/os ? compliance with pci spec ification revision 2.2 ? boundary-scan test ieee std. 1149.1 (jtag) compliant ? pin compatible packages across the proasic plus family unique clock condi tioning circuitry ? pll with flexible phase, multiply/divide and delay capabilities ? internal and/or external dynamic pll configuration ? two lvpecl differential pa irs for clock or data inputs standard fpga and asic design flow ? flexibility with choice of in dustry-standard front-end tools ? efficient design through front-e nd timing and gate optimization isp support ? in-system programming (isp) via jtag port srams and fifos ? smartgen netlist generation ensures optimal usage of embedded memory blocks ? 24 sram and fifo configurations with synchronous and asynchronous operation up to 150 mhz (typical) ? table 1 ? proasic plus product profile device apa075 apa150 apa300 1 apa450 apa600 1 apa750 apa1000 1 maximum system gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000 tiles (registers) 3,072 6,144 8,192 12,288 21,504 32,768 56,320 embedded ram bits (k=1,024 bits) 27 k 36k 72 k 108 k 126 k 144 k 198 k embedded ram blocks (256x9) 12 16 32 48 56 64 88 lvpecl 222 2 2 2 2 pll 222 2 2 2 2 global networks 4 4 4 4 4 4 4 maximum clocks 24 32 32 48 56 64 88 maximum user i/os 158 242 290 344 454 562 712 jtag isp yes yes yes yes yes yes yes pci yes yes yes yes yes yes yes package (by pin count) tqfp 100, 144 100 ? ? ? ? ? pqfp 208 208 208 208 208 208 208 pbga ? 456 456 456 456 456 456 fbga 144 144, 256 144, 256 144, 256, 484 256, 484, 676 676, 896 896, 1152 cqfp 2 208, 352 208, 352 208, 352 ccga/lga 2 624 624 notes: 1. available as commerci al/industrial and military/mil-std-883b devices. 2. these packages are available only for military/mil-std-883b devices. v5.8
proasic plus flash family fpgas ii v5.8 ordering information apa1000 fg _ part number speed grade blank = standard speed f f = 20% slower than standard package type pq = plastic quad flat pack (0.5 mm pitch) tq = thin quad flat pack (0.5 mm pitch) fg = fine pitch ball grid array (1.0 mm pitch) bg = plastic ball grid array (1.27 mm pitch) cq = ceramic quad flat pack (1.05 mm pitch) cg = ceramic column grid array (1.27 mm pitch) lg = land grid array (1.27 mm pitch) 1152 i package lead count application (ambient temperature range) g lead-free packaging blank = standard packaging g = rohs compliant packaging blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) pp = pre-production es = engineering silicon (room temperature only) m = military (-55?c to 125?c) b = mil-std-883 class b 150,000 equivalent system gates apa150 = 75,000 equivalent system gates apa075 = apa300 300,000 equivalent system gates = apa450 450,000 equivalent system gates = apa600 600,000 equivalent system gates = apa750 750,000 equivalent system gates = apa1000 1,000,000 equivalent system gates =
proasic plus flash family fpgas v5.8 iii device resources general guideline maximum performance numbers in this datasheet are based on characterized data. actel does not guarantee performance beyond the limits sp ecified within the datasheet. user i/os 2 commercial/industrial military/mil-std-883b device tqfp 100-pin tqfp 144-pin pqfp 208-pin pbga 456-pin fbga 144-pin fbga 256-pin fbga 484-pin fbga 676-pin fbga 896-pin fbga 1152-pin cqfp 208-pin cqfp 352-pin ccga/ lga 624-pin apa075 66 107 158 100 apa150 66 158 242 100 186 3 apa300 158 4 290 4 100 4 186 3, 4 158 248 apa450 158 344 100 186 3 344 3 apa600 158 4 356 4 186 3, 4 370 3 454 158 248 440 apa750 158 356 454 562 5 apa1000 158 4 356 4 642 4, 5 712 5 158 248 440 notes: 1. package definitions: tqfp = thin quad flat pack, pqfp = plastic quad flat pack, pbga = plastic ball grid array, fbga = fine p itch ball grid array, cqfp = ceramic quad flat pack, ccga = ce ramic column grid array, lga = land grid array 2. each pair of pecl i/os is counted as one user i/o. 3. fg256 and fg484 are footprint-compatible packages. 4. military temperature plastic package offering 5. fg896 and fg1152 are footprint-compatible packages.
proasic plus flash family fpgas iv v5.8 temperature grade offerings speed grade and temperature matrix package apa075 apa150 apa300 apa450 apa600 apa750 apa1000 tq100 c, i c, i tq144 c, i pq208 c, i c, i c, i, m c, i c, i, m c, i c, i, m bg456 c, i c, i, m c, i c, i, m c, i c, i, m fg144 c, i c, i c, i, m c, i fg256 c, i c, i, m c, i c, i, m fg484 c, i c, i, m fg676 c, i, m c, i fg896 c, i c, i, m fg1152 c, i cq208 m, b m, b m, b cq352 m, b m, b m, b cg624 m, b m, b note: c = commercial i = industrial m = military b = mil-std-883 ?f std. c ?? i ? m, b ? note: c = commercial i = industrial m = military b = mil-std-883
v5.8 v table of contents proasic plus flash family fpgas general description proasicplus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 timing control and characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 sample implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 adjustable clock delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 clock skew minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 pll electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 design environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 calculating typical power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 tristate buffer delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 output buffer delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47 input buffer delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 global input buffer delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 predicted global routing delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 global routing skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 module delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 sample macrocell library listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 embedded memory specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 6 recommended design practice for v pn /v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77 package pin assignments 100-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -1 144-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3 208-pin pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -5 208-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2 352-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 6 456-pin pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 144-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 256-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 484-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 676-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 896-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 1152-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 624-pin ccga/lga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 data sheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 export administration regulations (ear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 actel safety critical, life support, and high-re liability applications policy . . . . . 3-8

proasic plus flash family fpgas v5.8 1-1 general description the proasic plus family of devices, actel?s second- generation flash fpgas, offers enhanced performance over actel?s proasic family. it combines the advantages of asics with the benefits of programmable devices through nonvolatile flash technology. this enables engineers to creat e high-density systems using existing asic or fpga design flows and tools. in addition, the proasic plus family offers a unique clock conditioning circuit based on two on-board phase-locked loops (plls). the family offers up to one million system gates, supported with up to 198 kbit s of two-port sram and up to 712 user i/os, all providing 50 mhz pci performance. advantages to the de signer extend beyond performance. unlike sram-bas ed fpgas, four levels of routing hierarchy simplify rout ing, while the use of flash technology allows all functionality to be live at power- up. no external boot prom is required to support device programming. while on-board security mechanisms prevent access to th e program information, reprogramming can be performed in-system to support future design iterations and field upgrades. the device?s architecture mitigates the complexity of asic migration at higher user volume . this makes proasic plus a cost- effective solution for applic ations in the networking, communications, computing, and avionics markets. the proasic plus family achieves its nonvolatility and reprogrammability through an advanced flash-based 0.22 m lvcmos process with four layers of metal. standard cmos design techniques are used to implement logic and control functions, including the plls and lvpecl inputs. this results in predictable performance compatible with gate arrays. the proasic plus architecture provides granularity comparable to gate arrays. th e device core consists of a sea-of-tiles ? . each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropri ate flash switches. the combination of fine granul arity, flexible routing resources, and abundant flash switches allow 100% utilization and over 95% routability for highly congested designs. tiles and larger functions are interconnected through a four-level routing hierarchy. embedded two-port sram blocks with built-in fifo/ram control logic can have user-defined depths and widths. users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. the unique clock conditioning circuitry in each device includes two clock conditioning blocks. each block provides a pll core, delay lines, phase shifts (0 and 180 ), and clock multipliers/d ividers, as well as the circuitry needed to provide bidirectional access to the pll. the pll block contains four programmable frequency dividers which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. the clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). the pll can be configured internally or externally during operation without redesigning or reprogramming the part. in addition to the pll, there are two lvpecl differential input pairs to accommodate high-speed clock and data inputs. to support customer needs for more comprehensive, lower-cost, board-level testing, actel?s proasic plus devices are fully compatible with ieee standard 1149.1 for test access port and boundary-scan test architecture. for more information concerning the flash fpga implementation, please refer to the "boundary scan (jtag)" section on page 1-11 . proasic plus devices are available in a variety of high- performance plastic packages . those packages and the performance features discussed above are described in more detail in the following sections.
proasic plus flash family fpgas 1-2 v5.8 proasic plus architecture the proprietary proasic plus architecture provides granularity comparable to gate arrays. the proasic plus device core consists of a sea-of-tiles ( figure 1-1 ). each tile can be conf igured as a three-input logic function (e.g., nand gate, d-flip-flop, etc.) by programming the appr opriate flash switch interconnections ( figure 1-2 and figure 1-3 on page 1-3 ). tiles and larger functions ar e connected with any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. flash switches are programmed to connect signal lines to the appropriate logic cell inpu ts and outputs. dedicated high-performance lines are c onnected as needed for fast, low-skew global signal distribution throughout the core. maximum core utilization is possible for virtually any design. proasic plus devices also contain embedded, two-port sram blocks with built-i n fifo/ram control logic. programming options include synchronous or asynchronous operation, two-port ram configurations, user defined depth and width, and parity generation or checking. please see the "embedded memory configurations" section on page 1-23 for more information. figure 1-1 ? the proasic plus device architecture figure 1-2 ? flash switch 256x9 two-port sram or fifo block logic tile 256x9 two port sram or fifo block ram block ram block i/os sensing switching switch in switch out w ord floating gate
proasic plus flash family fpgas v5.8 1-3 live at power-up the actel flash-based proasic plus devices support level 0 of the live at power-up (lapu) classification standard. this feature he lps in system component initialization, executing cr itical tasks before the processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. the lapu feature of flash-based proasic plus devices greatly simplifies total system design and reduces total system cost, often elimin ating the need for complex programmable logic device (cpld) and clock generation plls that are used for th is purpose in a system. in addition, glitches and brow nouts in system power will not corrupt the proasic plus device's flash configuration, and unlike sram-based fpgas, the device will not have to be reloaded when syst em power is restored. this enables the reduction or complete removal of the configuration prom, expe nsive voltage monitor, brownout detection, and clock generator devices from the pcb design. flash-based proasic plus devices simplify total system design, and reduce cost and design risk, while increasing system relia bility and improving system initialization time. flash switch unlike sram fpgas, proasic plus uses a live-on-power-up isp flash switch as it s programming element. in the proasic plus flash switch, two transistors share the floating gate, which stores the programming information. one is the sens ing transistor, which is only used for writing and verification of the floating gate voltage. the other is the sw itching transistor. it can be used in the architecture to connect/separate routing nets or to configure logic. it is also used to erase the floating gate ( figure 1-2 on page 1-2 ). logic tile the logic tile cell ( figure 1-3 ) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). any three-input, one-output logic function (except a three-input xor) can be configured as one tile. the tile can be conf igured as a latch with clear or set or as a flip-flop with clear or set. thus, the tiles can flexibly map logic and sequential gates of a design. figure 1-3 ? core logic tile local routing in 1 in 2 (clk) in 3 (reset) efficient long-line routing
proasic plus flash family fpgas 1-4 v5.8 routing resources the routing structure of proasic plus devices is designed to provide high performance through a flexible four- level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. the ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles ( figure 1-4 ). the efficient long-line res ources provide routing for longer distances and higher fanout connections. these resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire proasic plus device ( figure 1-5 on page 1-5 ). each tile can drive signals onto the efficien t long-line resources, which can in turn access every input of every tile. active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. the high-speed, very long-lin e resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. ( figure 1-6 on page 1-6 ). the high-performance globa l networks are low-skew, high fanout nets that are accessible from external pins or from internal logic ( figure 1-7 on page 1-7 ). these nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. the global networks are implemented as clock trees, and signals can be introduced at any junction. these can be employed hierarchically with signals accessing every input on all tiles. figure 1-4 ? ultra-fast local resources l l l l l l inputs output ultra-fast local lines (connects a tile to the adjacent tile, i/o buffer, or memory block) l ll
proasic plus flash family fpgas v5.8 1-5 figure 1-5 ? efficient long-line resources l l llll l lllll l l llll l l llll l l llll logic cell spans 1 tile spans 2 tiles spans 4 tiles spans 1 tile spans 2 tiles spans 4 tiles logic tile
proasic plus flash family fpgas 1-6 v5.8 clock resources the proasic plus family offers powerful and flexible control of circuit timing through the use of analog circuitry. each chip has two clock conditioning blocks containing a phase-locked lo op (pll) core, delay lines, phase shifter (0 and 180 ), clock multiplier/dividers, and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the pll). this permits the pll block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). this circuitry is discussed in more detail in the "proasicplus clock management system" section on page 1-13 . clock trees one of the main architectural benefits of proasic plus is the set of power- and delay-friendly global networks. proasic plus offers four global trees. each of these trees is based on a network of spines and ribs that reach all the tiles in their regions ( figure 1-7 on page 1-7 ). this flexible clock tree architecture allows users to map up to 88 different internal/exter nal clocks in an apa1000 device. details on the clock spines and various numbers of the family are given in table 1-1 on page 1-7 . the flexible use of the proasic plus clock spine allows the designer to cope with severa l design requirements. users implementing clock-resource intensive applications can easily route external or gated internal clocks using global routing spines. users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. for design hints on using these features, refer to actel?s efficient use of proasic clock trees application note. figure 1-6 ? high-speed, very long-line resources pad ring pad ring pad ring i/o ring i/o ring high speed very long-line resouces sram sram
proasic plus flash family fpgas v5.8 1-7 note: this figure shows routing for only one global path. figure 1-7 ? high-performance global network table 1-1 ? clock spines apa075 apa150 apa300 apa450 apa600 apa750 apa1000 global clock networks (trees) 4 4 4 4 4 4 4 clock spines/tree 6 8 8 12 14 16 22 total spines 24 32 32 48 56 64 88 top or bottom spine height (tiles) 16 24 32 32 48 64 80 tiles in each top or bottom spine 512 768 1,024 1,024 1,536 2,048 2,560 total tiles 3,072 6,144 8,192 12,288 21,504 32,768 56,320 top spine bottom spine global pads global pads global networks global spine global ribs high-performance global network scope of spine (shaded area plus local rams and i/os) pad ring pad ring pad ring i/o ring i/o ring
proasic plus flash family fpgas 1-8 v5.8 array coordinates during many place-and-rout e operations in actel?s designer software tool, it is possible to set constraints that require array coordinates. table 1-2 is provided as a reference. the array coordinates are measured from the lower left (0,0). they can be used in region constraints for specific groups of core cells, i/os, and ram blocks. wild cards are also allowed. i/o and cell coordinates ar e used for placement constraints. two coordinate systems are needed because there is not a one-to-one correspondence between i/o cells and core cells. in addi tion, the i/o coordinate system changes depending on the di e/package combination. core cell coordinates start at the lower left corner (represented as (1,1)) or at (1,5) if memory blocks are present at the bottom. memory coordinates use the same system and are indicated in table 1-2 . the memory coordinates for an apa1000 are illustrated in figure 1-8 . for more information on how to use constraints, see the designer user?s guide or online help for proasic plus software tools. table 1-2 ? array coordinates device logic tile memory rows all min. max. bottom top xy x y y y min. max. apa075 1 1 96 32 ? (33,33) or (33, 35) 0,0 97, 37 apa150 1 1 128 48 ? (49,49) or (49, 51) 0,0 129, 53 apa300 1 5 128 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 129, 73 apa450 1 5 192 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 193, 73 apa600 1 5 224 100 (1,1) or (1,3) (101, 101) or (101, 103) 0,0 225, 105 apa750 1 5 256 132 (1,1) or (1,3) (133, 133) or (133, 135) 0,0 257, 137 apa1000 1 5 352 164 (1,1) or (1,3) (165, 165) or (165, 167) 0,0 353, 169 figure 1-8 ? core cell coordinates for the apa1000 (353,169) (352,167) (352,165) (352,164) (352,5) (352,3) (353,0) (352,1) (1,5) (1,1) (1,164) (1,165) (1,3) (1,167) (1,169) (0,0) core memory blocks memory blocks
proasic plus flash family fpgas v5.8 1-9 input/output blocks to meet complex system demands, the proasic plus family offers devices with a large number of user i/o pins, up to 712 on the apa1000. table 1-3 shows the available supply voltage conf igurations (the pll block uses an independent 2.5 v supply on the avdd and agnd pins). all i/os include es d protection circuits. each i/o has been tested to 2000 v to the human body model (per jesd22 (hbm)). six or seven standard i/o pads are grouped with a gnd pad and either a v dd (core power) or v ddp (i/o power) pad. two reference bias signals circle the chip. one protects the cascaded output drivers, while the other creates a virtual v dd supply for the i/o ring. i/o pads are fully configurab le to provide the maximum flexibility and speed. each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer ( figure 1-9 and table 1-4 ). table 1-3 ? proasic plus i/o power supply voltages v ddp 2.5 v 3.3 v input compatibility 2.5v 3.3v output drive 2.5v 3.3v figure 1-9 ? i/o block schematic representation 3.3v/2.5v signal control pull-up control pad y en a 3.3 v/2.5 v signal control drive strength and slew-rate control table 1-4 ? i/o features function description i/o pads configured as inputs ? selectable 2.5 v or 3.3 v threshold levels ? optional pull-up resistor ? optionally configurable as schmitt trigger input. the schmitt trigger input option can be configured as an input only, not a bidirectional buffer. this input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35 v. i/o macros with an ?s? in the standard i/o library have added schmitt capabilities. ? 3.3 v pci compliant (exc ept schmitt trigger inputs) i/o pads configured as outputs ? selectable 2.5 v or 3.3 v compliant output signals ? 2.5 v ? jedec jesd 8-5 ? 3.3 v ? jedec jesd 8-a (lvttl and lvcmos) ? 3.3 v pci compliant ? ability to drive lvttl and lvcmos levels ? selectable drive strengths ? selectable slew rates ? tristate i/o pads configured as bidirectional buffers ? selectable 2.5 v or 3.3 v compliant output signals ? 2.5 v ? jedec jesd 8-5 ? 3.3 v ? jedec jesd 8-a (lvttl and lvcmos) ? 3.3 v pci compliant ? optional pull-up resistor ? selectable drive strengths ? selectable slew rates ? tristate
proasic plus flash family fpgas 1-10 v5.8 power-up sequencing while proasic plus devices are live at power-up, the order of v dd and v ddp power-up is important during system start-up. v dd should be powered up simultaneously with v ddp on proasic plus devices. failure to follow these guidelines may result in und esirable pin behavior during system start-up. for more information, refer to actel?s power-up behavior of proasic plus devices application note. lvpecl input pads in addition to standard i/o pads and power pads, proasic plus devices have a single lvpecl input pad on both the east and west side s of the device, along with avdd and agnd pins to power the pll block. the lvpecl pad cell consists of an input buffer (containing a low voltage differential amplifier) and a signal and its complement, ppecl (i/p) (pec ln) and npecl (peclref). the lvpecl input pad cell differs from the standard i/o cell in that it is operated from v dd only. since it is exclusively an input, it requires no output signal, output enable signal, or output configuration bits. as a special high-speed differential input, it also does not require pull ups. recommended termination for lvpecl inputs is shown in figure 1-10 . the lvpecl pad cell compares voltages on the ppecl (i/p) pad (as illustrated in figure 1-11 ) and the npecl pad and sends the results to the global mux ( figure 1-14 on page 1-14 ). this high-speed, low-skew out put essentially controls the clock conditioning circuit. lvpecls are designed to meet lvpecl jedec receiver standard levels ( table 1-5 ). figure 1-10 ? recommended termination for lvpecl inputs figure 1-11 ? lvpecl high and low threshold values table 1-5 ? lvpecl receiver specifications symbol parameter min. max units v ih input high voltage 1.49 2.72 v v il input low voltage 0.86 2.125 v v id differential input voltage 0.3 v dd v + _ ppecl npecl from lvpecl driver data z = 50 0 z = 50 0 r = 100 2.72 2.125 1.49 0.86 voltage
proasic plus flash family fpgas v5.8 1-11 boundary scan (jtag) proasic plus devices are compatible with ieee standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective, board-level testing. the basic proasic plus boundary-scan logic circuit is composed of the tap (test access port), tap controller, test data registers, and instruction register ( figure 1-12 ). this circuit supports all manda tory ieee 1149.1 instructions (extest, sample/preload and bypass) and the optional idcode instruction ( table 1-6 ). each test section is accessed through the tap, which has five associated pins: tck (t est clock input), tdi and tdo (test data input and output), tms (test mode selector) and trst (test reset input). tms, tdi and trst are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundar y-scan test usage. actel recommends that a nominal 20 k pull-up resistor is added to tdo and tck pins. the tap controller is a four-b it state machine (16 states) that operates as shown in figure 1-13 on page 1-12 . the ?1?s and ?0?s represent the va lues that must be present at tms at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. proasic plus devices have to be programmed at least once for complete boundary-scan functionality to be available. prior to being programmed, extest is not available. if boundary-scan func tionality is required prior to programming, refer to online technical support on the actel website and s earch for proasic plus bsdl. figure 1-12 ? proasic plus jtag boundary scan test logic circuit device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers table 1-6 ? boundary-scan opcodes hex opcode extest 00 sample/preload 01 idcode 0f clamp 05 bypass ff table 1-6 ? boundary-scan opcodes hex opcode
proasic plus flash family fpgas 1-12 v5.8 the tap controller receives two control inputs (tms and tck) and generates control and clock signals for the rest of the test logic architec ture. on power-up, the tap controller enters the test-logi c-reset state. to guarantee a reset of the controller from any of the possible states, tms must remain high for five tck cycles. the trst pin may also be used to asyn chronously place the tap controller in the test-logic-reset state. proasic plus devices support three types of test data registers: bypass, device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device. this speeds up test data transfer to other devices in a test data path. the 32-bit device identification register is a shift register with four fields (lowest significant byte (lsb), id number, part number and version). the boundary-scan register observes and controls the state of each i/o pin. each i/o cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. the serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary- scan register chain, which st arts at the tdi pin and ends at the tdo pin. the parallel ports are connected to the internal core logic tile and the input, output, and control ports of an i/o buffer to capt ure and load data into the register to control or obse rve the logic state of each i/o. figure 1-13 ? tap controller state diagram test-logic reset run-test/ idle select-dr- scan capture-dr shift-dr exit-dr pause-dr exit2-dr update-dr select-ir- scan capture-ir shift-ir exit-ir pause-ir exit2-ir update-ir 1 1 1 0 1 0 00 1 1 00 00 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
proasic plus flash family fpgas v5.8 1-13 timing control and characteristics proasic plus clock management system proasic plus devices provide designers with very flexible clock conditioning capabilities. each member of the proasic plus family contains two phase-locked loop (pll) blocks which perform the following functions: ? clock phase adjustment via programmable delay (250 ps steps from ?7 ns to +8 ns) ? clock skew minimization ? clock frequency synthesis each pll has the following key features: ? input frequency range (f in ) = 1.5 to 180 mhz ? feedback frequency range (f vco ) = 24 to 180 mhz ? output frequency range (f out ) = 8 to 180 mhz ? output phase shif t = 0 and 180 ? output duty cycle = 50% ? low output jitt er (max at 25c) ?f vco <10 mhz. jitter 1% or better ? 10 mhz < f vco < 60 mhz. jitter 2% or better ?f vco > 60 mhz. jitter 1% or better note: jitter(ps) = jitter(%)* period for example: ? low power consumption ? 6.9 mw (max ? analog supply) + 7.0 w/mhz (max ? digital supply) physical implementation each side of the chip contains a clock conditioning circuit based on a 180 mhz pll block ( figure 1-14 on page 1- 14 ). two global multiplexed lines extend along each side of the chip to provide bidire ctional access to the pll on that side (neither mux can be connected to the opposite side's pll). each global line has optional lvpecl input pads (described below). the global lines may be driven by either the lvpecl global input pad or the outputs from the pll block, or both. each global line can be driven by a different output from the pll. unused global pins can be configured as regular i/os or left unconnected. they default to an input with pull-up. the two signals available to driv e the global networks are as follows ( figure 1-15 on page 1-15 , table 1-7 on page 1- 15 , and table 1-8 on page 1-16 ): global a (secondary clock) ? output from global mux a ? conditioned version of pll output (f out ) ? delayed or advanced ? divided version of either of the above ? further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay) 1 global b ? output from global mux b ? delayed or advanced version of f out ? divided version of either of the above ? further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay) 2 functional description each pll block contains four programmable dividers as shown in figure 1-14 on page 1-14 . these allow frequency scaling of the input clock signal as follows: ? the n divider divides the input clock by integer factors from 1 to 32. ? the m divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64. ? the two dividers together can implement any combination of multiplication and division resulting in a clock fre quency between 24 and 180 mhz exiting the pll core. this clock has a fixed 50% duty cycle. ? the output frequency of the pll core is given by the formula eq 1-1 (f ref is the reference clock frequency): f out = f ref * m/n eq 1-1 ? the third and fourth dividers (u and v) permit the signals applied to the global network to each be further divided by integer factors ranging from 1 to 4. the implementations shown in eq2 and eq3 enable the user to define a wide range of frequency multiplier and divisors. f glb = m/(n*u) eq 1-2 f gla = m/(n*v) eq 1-3 jitter in picoseconds at 100 mhz = 0.01 * (1/100e6) = 100 ps ? maximum acquisition time = 80 s for f vco > 40 mhz = 30 s for f vco < 40 mhz 1. this mode is available through the delay feature of th e global mux driver.
proasic plus flash family fpgas 1-14 v5.8 enable the user to define a wide range of frequency multipliers and divisors. the cl ock conditioning circuit can advance or delay the clock up to 8 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. the system also allows for the selection of output frequency clock phases of 0 and 180. prior to the application of si gnals to the rib drivers, they pass through programmable delay units, one per global network. these units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. not all po ssible combinat ions of input and output modes can be used. the degrees of freedom available in the bidirectional global pad system and in the clock conditioning circui t have been restricted. this avoids unnecessary and unwieldy design kit and software work. notes: 1. fbdly is a programmable delay line from 0 to 4 ns in 250 ps increments. 2. dlya and dlyb are programmable delay lines, each wi th selectable values 0 ps, 250 ps, 500 ps, and 4 ns. 3. obdiv will also divide the phase-shift since it takes place after the pll core. figure 1-14 ? pll block ? top-level view an d detailed pll block diagram avdd agnd gnd + - v dd external feedback signal gla glb dynamic configuration bits flash configuration bits 8 27 4 clock conditioning circuitry (top level view) global mux a out global mux b out see figure 1-15 on page 1-14 input pins to the pll glb gla u v pll core 0? 180? 0 1 6 7 5 4 2 delay line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns p+ p- clock from core (glint mode) clk 1 0 deskew delay 2.95 ns 1 2 3 delay line 0.25 ns to 4.00 ns, 16 steps, 0.25 ns increments 3 1 2 delay line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns clock from core (glint mode) clka extfb xdlysel bypass secondary bypass primary fivdiv[4:0] fbdiv[5:0] fbsel[1:0] oamux[1:0] dlya[1:0] dlyb[1:0] obdiv[1:0] obmux[2:0] oadiv[1:0] fbdly[3:0] n m clock conditioning circuitry detailed block diagram
proasic plus flash family fpgas v5.8 1-15 note: when a signal from an i/o tile is connected to the core, it cannot be connected to the global mux at the same time. figure 1-15 ? input connectors to proasic plus clock conditioning circuitry table 1-7 ? clock-conditioning circuitry mux settings mux datapath comments fbsel 1 internal feedback 2 internal feedback and advance clock using fbdly ?0.25 to ?4 ns in 0.25 ns increments 3 external feedback (extfb) xdlysel 0 feedback unchanged 1 deskew feedback by advancing clock by system delay fixed delay of -2.95 ns obmux glb 0 primary bypass, no divider 1 primary bypass, use divider 2 delay clock using fbdly +0.25 to +4 ns in 0.25 ns increments 4 phase shift clock by 0 5 reserved 6 phase shift clock by +180 7 reserved oamux gla 0 secondary bypass, no divider 1 secondary bypass, use divider 2 delay clock using fbdly +0.25 to +4 ns in 0.25 ns increments 3 phase shift clock by 0 configuration tile configuration tile pecl pad cell glmx gl std. pad cell std. pad cell std. pad cell gl npecl ppecl core package pins physical i/o buffers global mux external feedback global mux b out global mux a out legend physical pin data signals to the core data signals to the pll block data signals to the global mux control signals to the global mux
proasic plus flash family fpgas 1-16 v5.8 lock signal an active-high lock signal (added via the smartgen pll development tool) indicates that the pll has locked to the incoming clock signa l. the pll will acquire and maintain lock even when th ere is jitter on the incoming clock signal. the pll will maintain lock with an input jitter up to 5% of the input period, with a maximum of 5 ns. users can employ the lo ck signal as a soft reset of the logic driven by glb and/or gla. note if f in is not within specified frequencies, then both the f out and lock signal are indeterminate. pll configuration options the pll can be configured during design (via flash- configuration bits set in the programming bitstream) or dynamically during device op eration, thus eliminating the need to reprogram the device. the dynamic configuration bits are loaded into a serial-in/parallel-out shift register provided in the clock conditioning circuit. the shift register can be accessed either from user logic within the device or via the jtag port. another option is internal dynamic configuration via user-designed hardware. refer to actel's proasic plus pll dynamic reconfiguration using jtag application note for more information. for information on the clock conditioning circuit, refer to actel?s using proasic plus clock conditioning circuits application note. sample implementations frequency synthesis figure 1-16 on page 1-17 illustrates an example where the pll is used to multiply a 33 mhz external clock up to 133 mhz. figure 1-17 on page 1-17 uses two dividers to synthesize a 50 mhz output clock from a 40 mhz input reference clock. the input frequency of 40 mhz is multiplied by five and divided by four, giving an output clock (glb) frequency of 50 mhz. when dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay wi thin the operating frequency ranges of the pll. for example, in this case the input divider could have been two and the output divider also two, giving us a division of the input frequency by four to go with the feedback loop division (effective multiplication) by five. adjustable clock delay figure 1-18 on page 1-18 illustrates the delay of the input clock by employing one of the adjustable delay lines. this is easily done in proasic plus by bypassing the pll core entirely and using the output delay line. notice also that the output clock can be effectively advanced relative to the input clock by using the delay line in the feedback path. this is shown in figure 1-19 on page 1-18 . clock skew minimization figure 1-20 on page 1-19 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. the input clock is fe d to the reference clock input of the pll. the out put clock (gla) feeds a clock network. the feedback input to the pll uses a clock input delayed by a routing network. the p ll then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effe ctive skew be tween the two clocks. refer to actel's using proasic plus clock conditioning circuits application note for more information. table 1-8 ? clock-conditioning circuitry delay-line settings delay line delay value (ns) dlyb 00 1 +0.25 2 +0.50 3+4.0 dlya 00 1 +0.25 2 +0.50 3+4.0
proasic plus flash family fpgas v5.8 1-17 figure 1-16 ? using the pll 33 mh z in, 133 mhz out figure 1-17 ? using the pll 40 mh z in, 50 mhz out n m u v d d d d pll core external feedback global mux b out global mux a out glb gla 0 ? 180 ? 33 mhz 133 mhz 4 1 1 n m u v d d d d pll core external feedback global mux b out global mux a out glb gl a 0 ? 180 ? 40 mhz 50 mhz 5 4 1
proasic plus flash family fpgas 1-18 v5.8 figure 1-18 ? using the pll to delay the input clock figure 1-19 ? using the pll to advan ce the input clock n m u v d d d d pll core external feedback global mux b out global mux a out glb gl a 0 ? 180 ? 133 mhz 133 mhz 1 1 1 n m u v d d d d pll core external feedback global mux b out global mux a out glb gl a 0 ? 180 ? 133 mhz 133 mhz 1 1 1
proasic plus flash family fpgas v5.8 1-19 figure 1-20 ? using the pll for clock deskewing u v n m d d d d pll core external feedback global mux b out global mux a out gl b gl a 133 mhz 133 mhz /1 /1 d q q set clr off chip on chip reference clock 180? 0?
proasic plus flash family fpgas 1-20 v5.8 logic tile timing characteristics timing characteristics for proasic plus devices fall into three categories: family dependent, device dependent, and design dependent. the input and output buffer characteristics are co mmon to all proasic plus family members. internal routing de lays are device dependent. design dependency means that actual delays are not determined until after plac ement and routing of the user?s design are complete. delay values may then be determined by using the timer utility or by performing simulation with post-layout delays. critical nets and typical nets propagation delays are expres sed only for typical nets, which are used for initial design performance evaluation. critical net delays can th en be applied to the most timing-critical paths. critical nets are determined by net property assignment prior to place-and-route. refer to the actel designer user?s guide or online help for details on using constraints. timing derating since proasic plus devices are manufactured with a cmos process, device performance will vary with temperature, voltage, and process. minimum timing parameters reflect maximum operating voltage, minimum operating temperat ure, and optimal process variations. maximum timing parameters reflect minimum operating voltage, maximu m operating temperature, and worst-case process variations (within process specifications). the derating factors shown in table 1-9 should be applied to all timing data contained within this datasheet. all timing numbers listed in this datasheet represent sample timing characteristics of proasic plus devices. actual timing delay values are design-specific and can be derived from the timer tool in actel?s designer software after place-and-route. table 1-9 ? temperature and voltage derating factors (normalized to worst-case commercial, t j = 70c, v dd = 2.3 v) ?55c ?40c 0c 25c 70c 85c 110c 125c 135c 150c 2.3 v 0.840.860.910.941.001.021.051.131.181.27 2.5 v 0.810.820.870.900.950.981.011.091.131.21 2.7 v 0.770.790.830.860.910.930.961.041.081.16 notes: 1. the user can set the junction temperature in designer softwar e to be any integer value in the range of ?55c to 175c. 2. the user can set the core voltage in designer software to be any value between 1.4 v and 1.6 v.
proasic plus flash family fpgas v5.8 1-21 pll electrical specifications parameter value t j ?40c value t j > ?40c notes frequency ranges reference frequency f in (min.) 2.0 mhz 1.5 mhz clock conditioning circuitry (min.) lowest input frequency reference frequency f in (max.) 180 mhz 180 mhz clock conditioning circuitry (max.) highest input frequency osc frequency f vco (min.) 60 24 mhz lowest output frequency voltage controlled oscillator osc frequency f vco (max.) 180 180 mhz highest output frequency voltage controlled oscillator clock conditioning circuitry f out (min.) f in 40 = 18 mhz f in > 40 = 16 mhz 6 mhz lowest output frequency clock conditioning circuitry clock conditioning circuitry f out (max.) 180 180 mhz highest output frequency clock conditioning circuitry acquisition time from cold start acquisition time (max.) 80 s 30 sf vco 40 mhz acquisition time (max.) 80 s 80 sf vco > 40 mhz long term jitter peak-to-peak max.* temperature frequency mhz f vco < 10 1060 25c (or higher) 1% 2% 1% jitter(ps) = jitter(%)*period for example: jitter in picoseco nds at 100 mhz = 0.01 * (1/100e6) = 100 ps 0c 1.5% 2.5% 1% ?40c 2.5% 3.5% 1% ?55c 2.5% 3.5% 1% power consumption analog supply power (max.*) 6.9 mw per pll digital supply current (max.) 7 w/mhz duty cycle 50% 0.5% input jitter tolerance 5% input period (max. 5 ns) maximum jitter allowable on an input clock to acquire and maintain lock. note: *high clock frequencies (>60 mhz) under typical setup conditions
proasic plus flash family fpgas 1-22 v5.8 pll i/o constraints pll locking is guaranteed only when the following constraints are followed: table 1-10 ? pll i/o constraints t j ?40c value t j > ?40c i/o type pll locking is guaranteed only when using low drive strength and low slew rate i/o. pll locking may be inconsistent when using high drive strength or high slew rate i/os no constraints sso apa300 hermetic packages 8 sso with fin 180 mhz and outputs switching simultaneously plastic packages 16 sso apa600 hermetic packages 16 sso plastic packages 32 sso apa1000 hermetic packages 16 sso plastic packages 32 sso apa300 hermetic packages 12 sso with fin 50 mhz and half outputs switching on positive clock edge, half switching on the negative clock edge no less than 10nsec later plastic packages 20 sso apa600 hermetic packages 32 sso plastic packages 64 sso apa1000 hermetic packages 32 sso plastic packages 64 sso
proasic plus flash family fpgas v5.8 1-23 user security proasic plus devices have flashlock protection bits that, once programmed, block the entire programmed contents from being read externally. please refer to table 1-11 for details on the number of bits in the key for each device. if locked, the user can only reprogram the device employing the user-d efined security key. this protects the device from bei ng read back and duplicated. since programmed data is stored in nonvolatile memory cells (actually very small capa citors) rather than in the wiring, physical deconstruction cannot be used to compromise data. this type of security breach is further discouraged by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). this is the highest security provided in the industry. for more information, refer to actel?s design security in nonvolatile flash and antifuse fpgas white paper. embedded memory floorplan the embedded memory is lo cated across the top and bottom of the device in 256x9 blocks ( figure 1-1 on page 1-2 ). depending on the device, up to 88 blocks are available to support a variet y of memory configurations. each block can be programmed as an independent memory array or combined (using dedicated memory routing resources) to form larger, more complex memory configurations. a single me mory configuration could include blocks from both the top and bottom memory locations. embedded memory configurations the embedded memory in the proasic plus family provides great configuration flexibility ( table 1-12 ). each proasic plus block is designed and optimized as a two- port memory (one read, on e write). this provides 198 kbits of two-port and/or single port memory in the apa1000 device. each memory block can be configured as fifo or sram, with independent selection of synchronous or asynchronous read and write ports ( table 1-13 ). additional characteristics include programmable flags as well as parity checking and generation. figure 1-21 on page 1-25 and figure 1-22 on page 1-26 show the block diagrams of the basic sram and fifo blocks. table 1-14 on page 1-25 and table 1-15 on page 1-26 describe memory block sram and fifo interface signals, respectively. a single memory block is designed to operate at up to 150 mhz (s tandard speed grade typical conditions). each block is comprised of 256 9-bit words (one read port, one write po rt). the memory blocks may be cascaded in width and/or depth to create the desired memory organization. ( figure 1-23 on page 1-27 ). this provides optimal bit widths of 9 (one block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. refer to actel?s smartgen user?s guide for more information. figure 1-24 on page 1-27 gives an example of optimal memory usage. ten blocks with 23,040 bits have been used to generate three arra ys of various widths and depths. figure 1-25 on page 1-27 shows how ram blocks can be used in parallel to create extra read ports. in this example, using only 10 of the 88 available blocks of the apa1000 yields an effective 6,912 bits of multiple port ram. the actel smartgen so ftware facilitates building wider and deeper memory configurations for optimal memory usage. table 1-11 ? flashlock key size by device device key size apa075 79 bits apa150 79 bits apa300 79 bits apa450 119 bits apa600 167 bits apa750 191 bits apa1000 263 bits ? table 1-12 ? proasic plus memory configurations by device device bottom top maximum width maximum depth dwdw apa075 0 12 256 108 1,536 9 apa150 0 16 256 144 2,048 9 apa300 16 16 256 144 2,048 9 apa450 24 24 256 216 3,072 9 apa600 28 28 256 252 3,584 9
proasic plus flash family fpgas 1-24 v5.8 apa750 32 32 256 288 4,096 9 apa1000 44 44 256 396 5,632 9 table 1-13 ? basic memory configurations type write access read access parity library cell name ram asynchronous asynchronous checked ram256x9aa ram asynchronous asynchronous generated ram256x9aap ram asynchronous synchronous transparent checked ram256x9ast ram asynchronous synchronous transparent generated ram256x9astp ram asynchronous synchronous pipelined checked ram256x9asr ram asynchronous synchronous pipelined generated ram256x9asrp ram synchronous asynchronous checked ram256x9sa ram synchronous asynchronous generated ram256xsap ram synchronous synchronous transparent checked ram256x9sst ram synchronous synchronous transparent generated ram256x9sstp ram synchronous synchronous pipelined checked ram256x9ssr ram synchronous synchronous pipelined generated ram256x9ssrp fifo asynchronous asynchronous checked fifo256x9aa fifo asynchronous asynchronous generated fifo256x9aap fifo asynchronous synchronous transparent checked fifo256x9ast fifo asynchronous synchronous transparent generated fifo256x9astp fifo asynchronous synchronous pipelined checked fifo256x9asr fifo asynchronous synchronous pipelined generated fifo256x9asrp fifo synchronous asynchronous checked fifo256x9sa fifo synchronous asynchronous generated fifo256x9sap fifo synchronous synchronous transparent checked fifo256x9sst fifo synchronous synchronous transparent generated fifo256x9sstp fifo synchronous synchronous pipelined checked fifo256x9ssr fifo synchronous synchronous pipelined generated fifo256x9ssrp table 1-12 ? proasic plus memory configurations by device device bottom top maximum width maximum depth dwdw
proasic plus flash family fpgas v5.8 1-25 note: each ram block contains a multiplexer (called dmux) for each out put signal, increasing design efficiency. these dmux cells do n ot consume any core logic tiles and connect di rectly to high-speed routing resources be tween the ram blocks. they are used when ram blocks are cascaded and are automatically inserted by the software tools. figure 1-21 ? example sram block diagrams table 1-14 ? memory block sram interface signals sram signal bits in/out description wclks 1 in write clock used on synchronization on write side rclks 1 in read clock used on synchronization on read side raddr<0:7> 8 in read address rblkb 1 in read block select (active low) rdb 1 in read pulse (active low) waddr<0:7> 8 in write address wblkb 1 in write block select (active low) di<0:8> 9 in input data bits <0:8>, <8> can be used for parity in wrb 1 in write pulse (active low) do<0:8> 9 out output data bits <0:8>, <8> can be used for parity out rpe 1 out read parity error (active high) wpe 1 out write parity error (active high) parodd 1 in selects odd parity generation/d etect when high, even parity when low note: not all signals shown are used in all modes. sram (256x9) di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb rdb wblkb rblkb wclks rclks rpe parodd di <0:8> waddr <0:7> wrb wblkb parodd wpe wpe sram (256x9) di <0:8> do <0:8> waddr <0:7> wrb rdb wblkb rblkb wclks rpe parodd wpe raddr <0:7> parodd di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb rdb wblkb rblkb rclks rpe wpe do <0:8> raddr <0:7> rdb rblkb rclks rpe sync write and sync read ports async write and async read ports sync write and async read ports async write and sync read ports sram (256x9) sram (256x9)
proasic plus flash family fpgas 1-26 v5.8 note: each ram block contains a multiplexer (called dmux) for each out put signal, increasing design efficiency. these dmux cells do n ot consume any core logic tiles and connect di rectly to high-speed routing resources be tween the ram blocks. they are used when ram blocks are cascaded and are automatically inserted by the software tools. figure 1-22 ? basic fifo block diagrams table 1-15 ? memory block fifo interface signals fifo signal bits in/out description wclks 1 in write clock used for synchronization on write side rclks 1 in read clock used for synchronization on read side level <0:7> 8 in direct configuratio n implements static flag logic rblkb 1 in read block select (active low) rdb 1 in read pulse (active low) reset 1 in reset for fifo pointers (active low) wblkb 1 in write block select (active low) di<0:8> 9 in input data bits <0:8>, <8> will be generated parity if pargen is true wrb 1 in write pulse (active low) full, empty 2 out fifo flags. full prev ents write and empty prevents read eqth, geqth 2 out eqth is true when the fifo holds th e number of words specified by the level signal. geqth is true when the fifo holds (level) words or more do<0:8> 9 out output data bits <0:8>. <8> will be parity output if pargen is true. rpe 1 out read parity error (active high) wpe 1 out write parity error (active high) lgdep <0:2> 3 in configures depth of the fifo to 2 (lgdep+1) parodd 1 in parity generation/detect ? even when low, odd when high fifo (256x9) level<0:7> do <0:8> di<0:8> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth wclks rclks reset reset rpe wpe full empty eqth geqth do <0:8> rpe wpe full empty eqth geqth di <0:8> do <0:8> level <0:7> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> di <0:8> level <0:7> wrb rdb wblkb rblkb parodd lgdep<0:2> full empty eqth geqth rclks reset reset level<0:7> di<0:8> wrb rdb wblkb rblkb parodd lgdep<0:2> wclks do <0:8> fifo (256x9) fifo (256x9) fifo (256x9) sync write and sync read ports sync write and async read ports async write and sync read ports async write and async read ports
proasic plus flash family fpgas v5.8 1-27 figure 1-23 ? apa1000 memory block architecture figure 1-24 ? example showing memory arrays wi th different widths and depths figure 1-25 ? multi-port memory usage word depth word width 88 blocks 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9 word depth word width 1,024 words x 9 bits, 1 read, 1 write 512 words x 18 bits, 1 read, 1 write 256 words x 18 bits, 1 read, 1 write total memory blocks used = 10 total memory bits = 23,040 256 256 256 256 9 256 256 9 9 256 99 256 256 256 256 256 99 9 256 9 512 words x 9 bits, 4 read, 1 write 256 words x 9 bits, 2 read, 1 write total memory blocks used = 10 total memory bits = 6,912 word depth word width write port write port read ports 9 9 read ports 99 9 9 256 256 256 256 256 256 256
proasic plus flash family fpgas 1-28 v5.8 design environment the proasic plus family of fpgas is fully supported by both actel's libero ? integrated design environment (ide) and designer fpga development software. actel libero ide is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a sing le environment (see actel?s website for more information about libero ide ). libero ide includes synplify ? ae from synplicity?, viewdraw ? ae from mentor graphics ? , model sim ? hdl simulator from mentor graphics, waveformer lite? ae from synapticad ? , palace? ae physical synthesis from magma, and designer software from actel. palace is an effective tool when designing with proasic plus . palace ae physical synthesis from magma takes an edif netlist and optimizes the performance of proasic plus devices through a physical placement-driven process, ensuring that timi ng closure is easily achieved. actel's designer software is a place-and-route tool that provides a comprehensive suite of back-end support tools for fpga development. the designer software includes the following: ? timer ? a world-class integrated static timing analyzer and constraints editor that support timing-driven place-and-route ? netlistviewer ? a design netlist schematic viewer ? chipplanner ? a graphical floorplanner viewer and editor ? smartpower ? allows the designer to quickly estimate the power consumption of a design ? pineditor ? a graphical application for editing pin assignments and i/o attributes ? i/o attribute editor ? di splays all assigned and unassigned i/o macros and their attributes in a spreadsheet format with the designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. additionally, actel?s back-annotation flow is compatible with all the major simulators. another tool included in the designer software is the smartgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel's designer software is compatible with the most popular fpga design entry and verification tools from eda vendors, such as ment or graphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems. isp the user can generate *.bit or *.stp programming files from the designer software and can use these files to program a device. proasic plus devices can be progr ammed in-system. for more information on isp of proasic plus devices, refer to the in-system programming proasic plus devices and performing internal in-system programming using actel?s proasic plus devices application notes. prior to being programmed for the first time, the proasic plus device i/os are in a tristate condition with the pull-up resistor option enabled.
proasic plus flash family fpgas v5.8 1-29 related documents application notes efficient use of proasic clock trees http://www.actel.com/documen ts/a500k_clocktree_an.pdf i/o features in proasic plus flash fpgas http://www.actel.com/docum ents/apa_lvpecl_an.pdf power-up behavior of proasic plus devices http://www.actel.com/docum ents/apa_powerup_an.pdf proasic plus pll dynamic reconfiguration using jtag http://www.actel.com/documen ts/apa_plldynamic_an.pdf using proasic plus clock conditioning circuits http://www.actel.com/doc uments/apa_pll_an.pdf in-system programming proasic plus devices http://www.actel.com/documen ts/apa_external_isp_an.pdf performing internal in-system programming using actel?s proasic plus devices http://www.actel.com/documen ts/apa_microprocessor_an.pdf proasic plus ram and fifo blocks http://www.actel.com/docum ents/apa_ram_fifo_an.pdf white paper design security in nonvolatile flash and antifuse fpgas http://www.actel.com/documen ts/designsecurity_wp.pdf user?s guide designer user?s guide http://www.actel.com/doc uments/designer_ug.pdf smartgen cores reference guide http://www.actel.com/docum ents/gen_refguide_ug.pdf proasic and proasic plus macro library guide http://www.actel.com/docum ents/pa_libguide_ug.pdf additional information the following link contains addi tional information on proasic plus devices. http://www.actel.com/products/proasicplus/default.aspx
proasic plus flash family fpgas 1-30 v5.8 package thermal characteristics the proasic plus family is available in several package types with a range of pin counts. actel has selected packages based on high pin co unt, reliability factors, and superior thermal characteristics. thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package to the surrounding air. junction-to-ambient thermal resistance is measur ed in degrees celsius/watt and is represented as theta ja ( ja ). the lower the thermal resistance, the more efficiently a package will dissipate heat. a package?s maximum allowed power (p) is a function of maximum junction temperature (t j ), maximum ambient operating temperature (t a ), and junction-to-ambient thermal resistance ja . maximum junction temperature is the maximum allowable temperature on the active surface of the ic and is 110 c. p is defined as : eq 1-4 ja is a function of the rate (in linear feet per minute (lfpm)) of airflow in contact with the package. when the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. the maximum power dissipation allowed for a military temperature device is specified as a function of jc . the absolute maximum junction temperature is 150c. the calculation of the absolute maximum power dissipation allowed for a military temperature application is illustrated in the following example for a 456-pin pbga package: eq 1-5 p t j t a ? ja - - - - - - - - - - - - - - - - - - - = table 1-16 ? package thermal characteristics plastic packages pin count jc ja units still air 1.0 m/s 200 ft./min. 2.5 m/s 500 ft./min. thin quad flat pack (tqfp) 100 14.0 33.5 27.4 25.0 c/w thin quad flat pack (tqfp) 144 11.0 33.5 28.0 25.7 c/w plastic quad flat pack (pqfp) 1 208 8.0 26.1 22.5 20.8 c/w pqfp with heat spreader 2 208 3.8 16.2 13.3 11.9 c/w plastic ball grid array (pbga) 456 3.0 15.6 12.5 11.6 c/w fine pitch ball grid array (fbga) 144 3.8 26.9 22.9 21.5 c/w fine pitch ball grid array (fbga) 256 3.8 26.6 22.8 21.5 c/w fine pitch ball grid array (fbga) 3 484 3.2 18.0 14.7 13.6 c/w fine pitch ball grid array (fbga) 4 484 3.2 20.5 17.0 15.9 c/w fine pitch ball grid array (fbga) 676 3.2 16.4 13.0 12.0 c/w fine pitch ball grid array (fbga) 896 2.4 13.6 10.4 9.4 c/w fine pitch ball grid array (fbga) 1152 1.8 12.0 8.9 7.9 c/w ceramic quad flat pack (cqfp) 208 2.0 22.0 19.8 18.0 c/w ceramic quad flat pack (c qfp) 352 2.0 17.9 16.1 14.7 c/w ceramic column grid array (ccga/lga) 624 6.5 8.9 8.5 8.0 c/w notes: 1. valid for the following devices irrespective of temperature grade: apa075, apa150, and apa300 2. valid for the following devices irrespective of te mperature grade: apa450, apa600, apa750, and apa1000 3. depopulated array 4. full array maximum power allowed max. junction temp. ( c) max. case temp. ( c) ? jc ( c/w) ------------------------------------------------------------------------------------------------------------------------ 150 c 125 c ? 3.0 c/w ------------------------------------- - 8.333w = = =
proasic plus flash family fpgas v5.8 1-31 calculating typical power dissipation proasic plus device power is calculated with bo th a static and an acti ve component. the active component is a function of both the number of tile s utilized and the system speed. power dissip ation can be calculat ed using the following formula: total power consumption?p total p total = p dc + p ac where: global clock contribution?p clock p clock , the clock component of power dissipation, is given by the piece-wise model: for r < 15000 the model is: (p1 + (p2*r) - ( p7*r2)) * fs (lightly-loaded clock trees) for r > 15000 the model is: (p10 + p11*r) * fs (heavily-loaded clock trees) where: storage-tile contribution?p storage p storage , the storage-tile (registe r) component of ac power dissipation, is given by p storage = p5 * ms * fs where: p dc = 7 mw for the apa075 8 mw for the apa150 11 mw for the apa300 12 mw for the apa450 12 mw for the apa600 13 mw for the apa750 19 mw for the apa1000 p dc includes the stat ic components of p vddp + p vdd + p avdd p ac =p clock + p storage + p logic + p outputs + p inputs + p pll + p memory p1 = 100 w/mhz is the basic power consumption of the clock tree per mhz of the clock p2 = 1.3 w/mhz is the incremental power consumption of th e clock tree per storage tile ? also per mhz of the clock p7 = 0.00003 w/mhz is a correction fact or for partially-loaded clock trees p10 = 6850 w/mhz is the basic power consumption of the clock tree per mhz of the clock p11 = 0.4 w/mhz is the incremental power consumption of the clock tree pe r storage tile ? also per mhz of the clock r = the number of storage tile s clocked by this clock fs = the clock frequency p5 = 1.1 w/mhz is the average power consumption of a storage tile per mhz of its output toggling rate. the maximum output toggling rate is fs/2. ms = the number of storage tiles (reg ister) switching dur ing each fs cycle fs = the clock frequency
proasic plus flash family fpgas 1-32 v5.8 logic-tile contribution?p logic p logic , the logic-tile component of ac power dissipation, is given by p logic = p3 * mc * fs where: i/o output buffer contribution?p outputs p outputs , the i/o component of ac powe r dissipation, is given by p outputs = (p4 + (c load * v ddp 2 )) * p * fp where: i/o input buffer's buffer contribution?p inputs the input?s component of ac power dissipation is given by p inputs = p8 * q * fq where: pll contribution?p pll p pll = p9 * n pll where: ram contribution?p memory finally, p memory , the memory component of ac power consumption, is given by p memory = p6 * n memory * f memory * e memory where: p3 = 1.4 w/mhz is the average power consumption of a logi c tile per mhz of its ou tput toggling rate. the maximum output toggling rate is fs/2. mc = the number of logic tiles switching during each fs cycle fs = the clock frequency p4 = 326 w/mhz is the intrinsic power consumption of an output pad normalized per mhz of the output frequency. this is the total i/o current v ddp . c load = the output load p = the number of outputs fp = the average output frequency p8 = 29 w/mhz is the intrinsic power consumption of an input pad normalized per mhz of the input frequency. q = the number of inputs fq = the average input frequency p9 = 7.5 mw. this value has been estimated at maximum pll clock frequency. n pll = number of plls used p6 = 175 w/mhz is the average power consumption of a memory block per mhz of the clock n memory = the number of ram/fifo blocks (1 block = 256 words * 9 bits) f memory = the clock frequency of the memory e memory = the average number of active blocks divided by the total number of blocks (n) of the memory. ? typical values for e memory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8, 9, 16, and 32 memory configuration ? in addition, an application-dependent component to e memory can be considered. for example, for a 1kx8 memory configurat ion using only 1 cycle out of 2, e memory = 1/4*1/2 = 1/8
proasic plus flash family fpgas v5.8 1-33 the following is an apa750 exam ple using a shift register design with 13,440 storage tiles (register) and 0 logic tiles. this design has one clock at 10 mhz, a nd 24 outputs toggling at 5 mhz. we then calculate the various components as follows: p clock => p clock = (p1 + (p2*r) - (p7*r 2 )) * fs = 121.5 mw p storage => p storage = p5 * ms * fs = 147.8 mw p logic => p logic = 0 mw p outputs => p outputs = (p4 + (c load * v ddp 2 )) * p * fp = 91.4 mw p inputs => p inputs = p8 * q * fq = 0.3 mw p memory => p memory = 0 mw p ac => 361 mw p total p dc + p ac = 374 mw (typical) fs = 10 mhz r = 13,440 ms = 13,440 (in a shift register 100% of storage tile s are toggling at each cloc k cycle and fs = 10 mhz) mc = 0 (no logic tiles in this shift register) c load = 40 pf v ddp = 3.3 v p=24 fp = 5 mhz q=1 fq = 10 mhz n memory = 0 (no ram/fifo blocks in this shift register)
proasic plus flash family fpgas 1-34 v5.8 operating conditions standard and ?f parts are the same unless otherwise no ted. all ?f parts are only available as commercial. performance retention for devices operated and stored at 110c or less, the performance retention period is 20 years after programming. for devices operated and stored at temperatures greater than 110c, refer to table 1-19 on page 1-35 to determine the performance retention period. actel does not guar antee performance if the performance retention period is exceeded. designers can determine the performance retention period from the following table. evaluate the percentage of time spent at the highest temperature, then dete rmine the next highest temperature to which the device will be exposed. in table 1-19 on page 1-35 , find the temperature profile that most closely matches the application. example ? the ambient temperature of a system cycles between 100c (25% of the time) and 50c (75% of the time). no forced ventilation cooling system is in use. an apa600-pq208m fpga operates in the system, dissipating 1 w. the package thermal resistance (junction-to-ambient) in still air ja is 20c/w, indicating that the junction temperatur e of the fpga will be 120c (25% of the time) and 70c ( 75% of the time). the entry in table 1-19 on page 1-35 , which most closely matches the application, is 25% at 125c with 75% at 110c. performance retention in this example is at least 16.0 years. note that exceeding the st ated retention period may result in a performance degradation in the fpga below the worst-case performance in dicated in the actel timer. to ensure that performance does not degrade below the worst-case values in the actel timer, the fpga must be reprogrammed within the performance retention period. in addition, note that performance retention is independent of whether or not the fpga is operating. the retention period of a device in storage at a given temperature will be the same as the retention period of a device operating at that junction temperature. table 1-17 ? absolute maximum ratings* parameter condition minimum maximum units supply voltage core (v dd )?0.33.0v supply voltage i/o ring (v ddp )?0.34.0v dc input voltage ?0.3 v ddp + 0.3 v pci dc input voltage ?1.0 v ddp + 1.0 v pci dc input clamp current (absolute) v in < ?1 or v in = v ddp + 1 v 10 ma lvpecl input voltage ?0.3 v ddp + 0.5 v gnd 00v note: *stresses beyond those listed u nder ?absolute maximum ratings? may cause pe rmanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliab ility. devices should not be operated outside th e recommended operating conditions. table 1-18 ? programming, storage, and operating limits product grade programming cycles (min.) program retention (min.) storage temperature operating min. max. t j max. junction temperature commercial 500 20 years ?55c 110c 110c industrial 500 20 years ?55c 110c 110c military 100 refer to table 1-19 on page 1-35 ?65c 150c 150c mil-std-883 100 refer to table 1-19 on page 1-35 ?65c 150c 150c
proasic plus flash family fpgas v5.8 1-35 table 1-19 ? military temperature grade product performance retention minimum time at t j 110c or below minimum time at t j 125c or below minimum time at t j 135c or below minimum time at t j 150c or below minimum performance retention (years) 100% 20.0 90% 10% 18.2 75% 25% 16 90% 10% 15.4 50% 50% 13.3 90% 10% 11.8 75% 25% 11.4 100% 10 90% 10% 9.1 50% 50% 8 75% 25% 8 90% 10% 7.7 75% 25% 7.3 50% 50% 6.7 75% 25% 5.7 100% 5 90% 10% 4.5 50% 50% 4.4 50% 50% 4 75% 25% 4 50% 50% 3.3 100% 2.5
proasic plus flash family fpgas 1-36 v5.8 table 1-20 ? recommended maximum operating conditions programming and pll supplies parameter condition commercial/industrial/ military/mil-std-883 units minimum maximum v pp during programming 15.8 16.5 v normal operation 1 016.5v v pn during programming ?13.8 ?13.2 v normal operation 2 ?13.8 0.5 v i pp during programming 25 ma i pn during programming 10 ma avdd v dd v dd v agnd gnd gnd v notes: 1. please refer to the "vpp programming supply pin" section on page 1-77 for more information. 2. please refer to the "vpn programming supply pin" section on page 1-77 for more information. table 1-21 ? recommended operating conditions parameter symbol limits commercial industrial military/mil-std-883 dc supply voltage (2.5 v i/os) v dd and v ddp 2.5 v 0.2 v 2.5 v 0.2 v 2.5 v 0.2 v dc supply voltage (3.3 v i/os) v ddp v dd 3.3 v 0.3 v 2.5 v 0.2 v 3.3 v 0.3 v 2.5 v 0.2 v 3.3 v 0.3 v 2.5 v 0.2 v operating ambient temperature range t a , t c 0c to 70c ?40c to 85c ?55c (t a ) to 125c (t c ) maximum operating junction temperature t j 110c 110c 150c note: for i/o long-term reliability, external pull-up resistor s cannot be used to increase output voltage above v ddp .
proasic plus flash family fpgas v5.8 1-37 table 1-22 ? dc electrical specifications (v ddp = 2.5 v 0.2v) symbol parameter conditions commercial/industrial/ military/mil-std-883 1, 2 min. typ. max. units v oh output high voltage high drive (ob25lph) low drive (ob25lpl) i oh = ?6 ma i oh = ?12 ma i oh = ?24 ma i oh = ?3 ma i oh = ?6 ma i oh = ?8 ma 2.1 2.0 1.7 2.1 1.9 1.7 v v ol output low voltage high drive (ob25lph) low drive (ob25lpl) i ol = 8 ma i ol = 15 ma i ol = 24 ma i ol = 4 ma i ol = 8 ma i ol = 15 ma 0.2 0.4 0.7 0.2 0.4 0.7 v v ih 6 input high voltage 1.7 v ddp + 0.3 v v il 7 input low voltage ?0.3 0.7 v r weakpullup weak pull-up resistance (otb25lpu) v in 1.25 v 6 56 k hyst input hysteresis schmitt see table 1-4 on page 1-9 0.3 0.35 0.45 v i in input current with pull up (v in = gnd) ?240 ? 20 a without pull up (v in = gnd or v dd ) ?10 10 a i ddq quiescent supply current (standby) commercial v in = gnd 4 or v dd std. 5.0 15 ma ?f 3 5.0 25 ma i ddq quiescent supply current (standby) industrial v in = gnd 4 or v dd std. 5.0 20 ma i ddq quiescent supply current (standby) military/mil-std-883 v in = gnd 4 or v dd std. 5.0 25 ma i oz tristate output leakage current v oh = gnd or v dd std. ?10 10 a ?f 3, 5 ?10 100 a notes: 1. all process conditions. commercial/industrial: junction temperature: ?40 to +110c. 2. all process conditions. military: junction temperature: ?55 to +150c. 3. all ?f parts are available only as commercial. 4. no pull-up resistor. 5. this will not exceed 2 ma total per device. 6. during transitions, the input signal may overshoot to v ddp +1.0v for a limited time of no larger than 10% of the duty cycle. 7. during transitions, the input signal may undershoot to -1.0 v for a limited time of no larger than 10% of the duty cycle.
proasic plus flash family fpgas 1-38 v5.8 i osh output short circuit current high high drive (ob25lph) low drive (ob25lpl) v in = v ss v in = v ss ?120 ?100 ma i osl output short circuit current low high drive (ob25lph) low drive (ob25lpl) v in = v ddp v in = v ddp 100 30 ma c i/o i/o pad capacitance 10 pf c clk clock input pad capacitance 10 pf table 1-22 ? dc electrical specifications (v ddp = 2.5 v 0.2v) (continued) symbol parameter conditions commercial/industrial/ military/mil-std-883 1, 2 min. typ. max. units notes: 1. all process conditions. commercial/industrial: junction temperature: ?40 to +110c. 2. all process conditions. military: junction temperature: ?55 to +150c. 3. all ?f parts are available only as commercial. 4. no pull-up resistor. 5. this will not exceed 2 ma total per device. 6. during transitions, the input signal may overshoot to v ddp +1.0v for a limited time of no larger than 10% of the duty cycle. 7. during transitions, the input signal may undershoot to -1.0 v for a limited time of no larger than 10% of the duty cycle.
proasic plus flash family fpgas v5.8 1-39 table 1-23 ? dc electrical specifications (v ddp = 3.3 v 0.3 v and v dd = 2.5 v 0.2 v) applies to commercial and industrial temperature only symbol parameter conditions commercial/industrial 1 units min. typ. max. v oh output high voltage 3.3 v i/o, high drive (ob33p) 3.3 v i/o, low drive (ob33l) i oh = ?14 ma i oh = ?24 ma i oh = ?6 ma i oh = ?12 ma 0.9 ? v ddp 2.4 0.9 ? v ddp 2.4 v v ol output low voltage 3.3 v i/o, high drive (ob33p) 3.3 v i/o, low drive (ob33l) i ol = 15 ma i ol = 20 ma i ol = 28 ma i ol = 7 ma i ol = 10 ma i ol = 15 ma 0.1v ddp 0.4 0.7 0.1v ddp 0.4 0.7 v v ih 5 input high voltage 3.3 v schmitt trigger inputs 3.3 v lvttl/lvcmos 2.5 v mode 1.6 2 1.7 v ddp + 0.3 v ddp + 0.3 v ddp + 0.3 v v il 6 input low voltage 3.3 v schmitt trigger inputs 3.3 v lvttl/lvcmos 2.5 v mode ?0.3 ?0.3 ?0.3 0.8 0.8 0.7 v r weakpullup weak pull-up resistance (iob33u) v in 1.5 v 7 43 k r weakpullup weak pull-up resistance (iob25u) v in 1.5 v 7 43 k i in input current with pull up (v in = gnd) ?300 ?40 a without pull up (v in = gnd or v dd ) ?10 10 a i ddq quiescent supply current (standby) commercial v in = gnd 3 or v dd std. 5.015ma ?f 2 5.0 25 ma i ddq quiescent supply current (standby) industrial v in = gnd 3 or v dd std. 5.0 20 ma i ddq quiescent supply current (standby) military v in = gnd 3 or v dd std. 5.0 25 ma notes: 1. all process conditions. commercial/industri al: junction temperature: ?40 to +110c. 2. all ?f parts are only available as commercial. 3. no pull-up resistor required. 4. this will not exceed 2 ma total per device. 5. during transitions, the inpu t signal may overshoot to v ddp +1.0 v for a limited time of no larger than 10% of the duty cycle. 6. during transitions, the input signal may undershoot to ?1.0 v for a limited time of no larger than 10% of the duty cycle.
proasic plus flash family fpgas 1-40 v5.8 i oz tristate output leakage current v oh = gnd or v dd std. ?10 10 a ?f 2, 4 ?10 100 a i osh output short circuit current high 3.3 v high drive (ob33p) 3.3 v low drive (ob33l) v in = gnd v in = gnd ?200 ?100 i osl output short circuit current low 3.3 v high drive 3.3 v low drive v in = v dd v in = v dd 200 100 c i/o i/o pad capacitance 10 pf c clk clock input pad capacitance 10 pf table 1-23 ? dc electrical specifications (v ddp = 3.3 v 0.3 v and v dd = 2.5 v 0.2 v) (continued) applies to commercial and industrial temperature only symbol parameter conditions commercial/industrial 1 units min. typ. max. notes: 1. all process conditions. commercial/industri al: junction temperature: ?40 to +110c. 2. all ?f parts are only available as commercial. 3. no pull-up resistor required. 4. this will not exceed 2 ma total per device. 5. during transitions, the inpu t signal may overshoot to v ddp +1.0 v for a limited time of no larger than 10% of the duty cycle. 6. during transitions, the input signal may undershoot to ?1.0 v for a limited time of no larger than 10% of the duty cycle.
proasic plus flash family fpgas v5.8 1-41 table 1-24 ? dc electrical specifications (v ddp = 3.3 v 0.3 v and v dd = 2.5 v 0.2 v) applies to military temperature and mil-std-883b temperature only symbol parameter conditions military/mil-std-883b 1 units min. typ. max. v oh output high voltage 3.3 v i/o, high drive, high slew (ob33ph) 3.3v i/o, high drive, normal/ low slew (ob33pn/ob33pl) 3.3 v i/o, low drive , high/ normal/low slew (ob33lh/ ob33ln/ob33ll) i oh = ?8 ma i oh = ?16 ma i oh = ?3ma i oh = ?8ma i oh = ?3 ma i oh = ?8 ma 0.9 ? v ddp 2.4 0.9 ? v ddp 2.4 0.9 ? v ddp 2.4 v v ol output low voltage 3.3 v i/o, high drive, high slew (ob33ph) 3.3v i/o, high drive, normal/ low slew (ob33pn/ob33pl)) 3.3 v i/o, low drive, high/ normal/low slew (ob33lh/ ob33ln/ob33ll) i ol = 12 ma i ol = 17 ma i ol = 28 ma i ol = 4 ma i ol = 6 ma i ol = 13 ma i ol = 4 ma i ol = 6 ma i ol = 13 ma 0.1v ddp 0.4 0.7 0.1v ddp 0.4 0.7 0.1v ddp 0.4 0.7 v v ih 4 input high voltage 3.3 v schmitt trigger inputs 3.3 v lvttl/lvcmos 2.5 v mode 1.6 2 1.7 v ddp + 0.3 v ddp + 0.3 v ddp + 0.3 v v il 5 input low voltage 3.3 v schmitt trigger inputs 3.3 v lvttl/lvcmos 2.5 v mode ?0.3 ?0.3 ?0.3 0.7 0.8 0.7 v r weakpullup weak pull-up resistance (iob33u) v in 1.5 v 7 43 k r weakpullup weak pull-up resistance (iob25u) v in 1.5 v 7 43 k i in input current with pull up (v in = gnd) ?300 ?40 a without pull up (v in = gnd or v dd ) ?10 10 a i ddq quiescent supply current (standby) commercial v in = gnd 2 or v dd std. 5.015ma ?f 5.0 25 ma notes: 1. all process conditions. military temperature / mil-std -883 class b: junction temperature: ?55 to +125c. 2. no pull-up resistor required. 3. this will not exceed 2 ma total per device. 4. during transitions, the inpu t signal may overshoot to v ddp +1.0 v for a limited time of no larger than 10% of the duty cycle. 5. during transitions, the input signal may undershoot to ?1.0 v for a limited time of no larger than 10% of the duty cycle.
proasic plus flash family fpgas 1-42 v5.8 i ddq quiescent supply current (standby) industrial v in = gnd 2 or v dd std. 5.0 20 ma i ddq quiescent supply current (standby) military v in = gnd 2 or v dd std. 5.0 25 ma i oz tristate output leakage current v oh = gnd or v dd std. ?10 10 a ?f 3 ?10 100 a i osh output short circuit current high 3.3 v high drive (ob33p) 3.3 v low drive (ob33l) v in = gnd v in = gnd ?200 ?100 i osl output short circuit current low 3.3 v high drive 3.3 v low drive v in = v dd v in = v dd 200 100 c i/o i/o pad capacitance 10 pf c clk clock input pad capacitance 10 pf table 1-24 ? dc electrical specifications (v ddp = 3.3 v 0.3 v and v dd = 2.5 v 0.2 v) (continued) applies to military temperature and mil-std-883b temperature only symbol parameter conditions military/mil-std-883b 1 units min. typ. max. notes: 1. all process conditions. military temperature / mil-std -883 class b: junction temperature: ?55 to +125c. 2. no pull-up resistor required. 3. this will not exceed 2 ma total per device. 4. during transitions, the inpu t signal may overshoot to v ddp +1.0 v for a limited time of no larger than 10% of the duty cycle. 5. during transitions, the input signal may undershoot to ?1.0 v for a limited time of no larger than 10% of the duty cycle.
proasic plus flash family fpgas v5.8 1-43 table 1-25 ? dc specifications (3.3 v pci operation) 1 symbol parameter condition commercial/ industrial 2,3 military/mil-std- 883 2,3 units min. max. min. max. v dd supply voltage for core 2.3 2.7 2.3 2.7 v v ddp supply voltage for i/o ring 3.0 3.6 3.0 3.6 v v ih input high voltage 0.5v ddp v ddp + 0.5 0.5v ddp v ddp + 0.5 v v il input low voltage ?0.5 0.3v ddp ?0.5 0.3v ddp v i ipu input pull-up voltage 4 0.7v ddp 0.7v ddp v i il input leakage current 5 0 < v in < v ddp std. ?10 10 ?50 50 a ?f 3, 6 ?10 100 a v oh output high voltage i out = ?500 a 0.9v ddp 0.9v ddp v v ol output low voltage i out = 1500 a 0.1v ddp 0.1v ddp v c in input pin capacitance (except clk) 10 10 pf c clk clk pin capacitance 5 12 5 12 pf notes: 1. for pci operation, use gl33, otb33ph, ob33ph, iob 33ph, ib33, or ib33s macro library cell only. 2. all process conditions. junction temperature: ?40 to +110c fo r commercial and industrial devices and ?55 to +125c for milit ary. 3. all ?f parts are available as commercial only. 4. this specification is guaranteed by design. it is the minimum voltage to which pull-up resistor s are calculated to pull a flo ated network. designers with applications sensit ive to static power utilization should ensu re that the input buffer is conducting mi nimum current at this input voltage. 5. input leakage currents include hi-z output leakage fo r all bidirectional buffers with tristate outputs. 6. the sum of the leakage currents for all inputs shall not exceed 2ma per device.
proasic plus flash family fpgas 1-44 v5.8 table 1-26 ? ac specifications (3.3 v pci revision 2.2 operation) symbol parameter condition commercial/industrial/m ilitary/mil-std- 883 units min. max. i oh(ac) switching current high 0 < v out 0.3v ddp * ?12v ddp ma 0.3v ddp v out < 0.9v ddp * (?17.1 + (v ddp ? v out )) ma 0.7v ddp < v out < v ddp * see equation c ? page 124 of the pci specification document rev. 2.2 (test point) v out = 0.7v ddp * ?32v ddp ma i ol(ac) switching current low v ddp > v out 0.6v ddp * 16v ddp ma 0.6v ddp > v out > 0.1v ddp 1 (26.7v out )ma 0.18v ddp > v out > 0 * see equation d ? page 124 of the pci specification document rev. 2.2 (test point) v out = 0.18v ddp 38v ddp ma i cl low clamp current ?3 < v in ?1 ?25 + (v in + 1)/0.015 ma i ch high clamp current v ddp + 4 > v in v ddp + 1 25 + (v in ? v ddp ? 1)/0.015 ma slew r output rise slew rate 0.2v ddp to 0.6v ddp load * 14v/ns slew f output fall slew rate 0.6v ddp to 0.2v ddp load * 14v/ns note: * refer to the pci specification document rev. 2.2. pin output buffer 1/2 in. max 10 pf 1k pin output buffer 10 pf 1k pad loading applicable to the rising edge pci pad loading applicable to the falling edge pci
proasic plus flash family fpgas v5.8 1-45 tristate buffer delays figure 1-26 ? tristate buffer delays table 1-27 ? worst-case commercial conditions v ddp = 3.0 v, v dd = 2.3 v, 35 pf load, t j = 70c macro type description max t dlh 1 max t dhl 2 max t enzh 3 max t enzl 4 units std. ?f std. ?f std. ?f std. ?f otb33ph 3.3 v, pci output current, high slew rate 2.0 2.4 2.2 2.6 2.2 2.6 2.0 2.4 ns otb33pn 3.3 v, high output current, nominal slew rate 2.2 2.6 2.9 3.5 2.4 2.9 2.1 2.5 ns otb33pl 3.3 v, high output current, low slew rate 2.5 3.0 3.2 3.9 2.7 3.3 2.8 3.4 ns otb33lh 3.3 v, low output current, high slew rate 2.6 3.1 4.0 4.8 2.8 3.4 3.0 3.6 ns otb33ln 3.3 v, low output current, nominal slew rate 2.9 3.5 4.3 5.2 3.2 3.8 4.1 4.9 ns otb33ll 3.3 v, low output current, lo w slew rate 3.0 3.6 5.6 6.7 3.3 3.9 5.5 6.6 ns notes: 1. t dlh =data-to-pad high 2. t dhl =data-to-pad low 3. t enzh =enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low 5. all ?f parts are only available as commercial. table 1-28 ? worst-case commercial conditions v ddp = 2.3 v, v dd = 2.3 v, 35 pf load, t j = 70c macro type description max t dlh 1 max t dhl 2 max t enzh 3 max t enzl 4 units std. ?f std. ?f std. ?f std. ?f otb25lphh 2.5 v, low power, high output current, high slew rate 5 2.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4 ns otb25lphn 2.5 v, low power, high output current, nominal slew rate 5 2.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5 ns otb25lphl 2.5 v, low power, high output current, low slew rate 5 2.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2 ns otb25lplh 2.5 v, low power, low output current, high slew rate 5 2.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1 ns notes: 1. t dlh =data-to-pad high 2. t dhl =data-to-pad low 3. t enzh =enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low 5. low power i/o work with v ddp =2.5 v 10% only. v ddp =2.3 v for delays. 6. all ?f parts are only available as commercial. pa d a otbx a 50% pad v ol v oh 50% t dlh 50% 50% t dhl en 50% pad v ol 50% t enzl 50% 10% en 50% pad gnd v oh 50% t enzh 50% 90% v ddp 35pf en
proasic plus flash family fpgas 1-46 v5.8 otb25lpln 2.5 v, low power, low output current, nominal slew rate 5 3.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6 ns otb25lpll 2.5 v, low power, low output current, low slew rate 5 4.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1 ns table 1-29 ? worst-case military conditions v ddp = 3.0 v, v dd = 2.3 v, 35 pf load, t j = 125c for military/mil-std-883 macro type description max t dlh 1 max t dhl 2 max t enzh 3 max t enzl 4 units std. std. std. std. otb33ph 3.3 v, pci output current, high slew rate 2.2 2.4 2.3 2.1 ns otb33pn 3.3 v, high output current, nominal slew rate 2.4 3.2 2.7 2.3 ns otb33pl 3.3 v, high output current, low slew rate 2.7 3.5 2.9 3.0 ns otb33lh 3.3 v, low output current, high slew rate 2.7 4.3 3.0 3.1 ns otb33ln 3.3 v, low output current, nominal slew rate 3.3 4.7 3.4 4.4 ns otb33ll 3.3 v, low output curren t, low slew rate 3.2 6.0 3.5 5.9 ns notes: 1. t dlh =data-to-pad high 2. t dhl =data-to-pad low 3. t enzh =enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low table 1-30 ? worst-case military conditions v ddp = 2.3 v, v dd = 2.3 v, 35 pf load, t j = 125c for military/mil-std-883 macro type description max t dlh 1 max t dhl 2 max t enzh 3 max t enzl 4 units std. std. std. std. otb25lphh 2.5 v, low power, high output current, high slew rate 5 2.3 2.3 2.4 2.1 ns otb25lphn 2.5 v, low power, high output current, nominal slew rate 5 2.7 3.2 2.8 2.1 ns otb25lphl 2.5 v, low power, high output current, low slew rate 5 3.2 3.5 3.3 2.8 ns otb25lplh 2.5 v, low power, low output current, high slew rate 5 3.0 5.0 3.2 2.8 ns otb25lpln 2.5 v, low power, low output current, nominal slew rate 5 3.7 4.5 4.1 4.1 ns otb25lpll 2.5 v, low power, low output current, low slew rate 5 4.4 5.8 4.4 5.4 ns notes: 1. t dlh =data-to-pad high 2. t dhl =data-to-pad low 3. t enzh =enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low 5. low power i/o work with v ddp =2.5v 10% only. v ddp =2.3v for delays. table 1-28 ? worst-case commercial conditions v ddp = 2.3 v, v dd = 2.3 v, 35 pf load, t j = 70c macro type description max t dlh 1 max t dhl 2 max t enzh 3 max t enzl 4 units std. ?f std. ?f std. ?f std. ?f notes: 1. t dlh =data-to-pad high 2. t dhl =data-to-pad low 3. t enzh =enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low 5. low power i/o work with v ddp =2.5 v 10% only. v ddp =2.3 v for delays. 6. all ?f parts are only available as commercial.
proasic plus flash family fpgas v5.8 1-47 output buffer delays figure 1-27 ? output buffer delays table 1-31 ? worst-case commercial conditions v ddp = 3.0 v, v dd = 2.3 v, 35 pf load, t j = 70c macro type description max t dlh 1 max t dhl 2 units std. ?f std. ?f ob33ph 3.3 v, pci output current, high slew rate 2.0 2.4 2.2 2.6 ns ob33pn 3.3 v, high output current, nominal slew rate 2.2 2.6 2.9 3.5 ns ob33pl 3.3 v, high output current, low slew rate 2.5 3.0 3.2 3.9 ns ob33lh 3.3 v, low output current, high slew rate 2.6 3.1 4.0 4.8 ns ob33ln 3.3 v, low output current, nominal slew rate 2.9 3.5 4.3 5.2 ns ob33ll 3.3 v, low output current, low slew rate 3.0 3.6 5.6 6.7 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low 3. all ?f parts are only available as commercial. table 1-32 ? worst-case commercial conditions v ddp = 2.3 v, v dd = 2.3 v, 35 pf load, t j = 70c macro type description max t dlh 1 max t dhl 2 units std. ?f std. ?f ob25lphh 2.5 v, low power, high ou tput current, high slew rate 3 2.0 2.4 2.1 2.6 ns ob25lphn 2.5 v, low power, high ou tput current, nominal slew rate 3 2.4 2.9 3.0 3.6 ns ob25lphl 2.5 v, low power, high output current, low slew rate 3 2.9 3.5 3.2 3.8 ns ob25lplh 2.5 v, low power, low output current, high slew rate 3 2.7 3.3 4.6 5.5 ns ob25lpln 2.5 v, low power, low output current, nominal slew rate 3 3.5 4.2 4.2 5.1 ns ob25lpll 2.5 v, low power, low output current, low slew rate 3 4.0 4.8 5.3 6.4 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low 3. low-power i/os work with v ddp =2.5 v 10% only. v ddp =2.3 v for delays. 4. all ?f parts are only available as commercial. pad a 50% pad v ol v oh 50% t dlh 50% 50% t dhl 35pf a obx
proasic plus flash family fpgas 1-48 v5.8 table 1-33 ? worst-case military conditions v ddp = 3.0v, v dd = 2.3v, 35 pf load, t j = 125c for mili tary/mil-std-883 macro type description max. t dlh 1 max. t dhl 2 units std. std. ob33ph 3.3v, pci output current, high slew rate 2.1 2.3 ns ob33pn 3.3v, high output current, nominal slew rate 2.5 3.2 ns ob33pl 3.3v, high output current, low slew rate 2.7 3.5 ns ob33lh 3.3v, low output current, high slew rate 2.7 4.3 ns ob33ln 3.3v, low output current, nominal slew rate 3.3 4.7 ns ob33ll 3.3v, low output current, low slew rate 3.3 6.1 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low table 1-34 ? worst-case military conditions v ddp = 2.3 v, v dd = 2.3v, 35 pf load, t j = 125c for military/mil-std-883 macro type description max. t dlh 1 max. t dhl 2 units std. std. ob25lphh 2.5v, low power, high output current, high slew rate 3 2.3 2.4 ns ob25lphn 2.5v, low power, high output current, nominal slew rate 3 2.7 3.3 ns ob25lphl 2.5v, low power, high output current, low slew rate 3 3.2 3.5 ns ob25lplh 2.5v, low power, low output current, high slew rate 3 3.0 5.0 ns ob25lpln 2.5v, low power, low output current, nominal slew rate 3 3.9 4.6 ns ob25lpll 2.5v, low power, low output current, low slew rate 3 4.3 5.7 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low 3. low power i/o work with v ddp =2.5v 10% only. v ddp =2.3v for delays.
proasic plus flash family fpgas v5.8 1-49 input buffer delays figure 1-28 ? input buffer delays table 1-35 ? worst-case commercial conditions v ddp = 3.0 v, v dd = 2.3 v, t j = 70c macro type description max. t inyh 1 max. t inyl 2 units std. ?f std. ?f ib33 3.3 v, cmos input levels 3 , no pull-up resistor 0.4 0.5 0.6 0.7 ns ib33s 3.3 v, cmos input levels 3 , no pull-up resistor, schmitt trigger 0.6 0.7 0.8 0.9 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. lvttl delays are the same as cmos delays. 4. for lp macros, v ddp =2.3 v for delays. 5. all ?f parts are only available as commercial. table 1-36 ? worst-case commercial conditions v ddp = 2.3 v, v dd = 2.3 v, t j = 70c macro type description max. t inyh 1 max. t inyl 2 units std. ?f std. ?f ib25lp 2.5 v, cmos input levels 3 , low power 0.9 1.1 0.6 0.8 ns ib25lps 2.5 v, cmos input levels 3 , low power, schmitt trigger 0.7 0.9 0.9 1.1 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. lvttl delays are the same as cmos delays. 4. for lp macros, v ddp =2.3 v for delays. 5. all ?f parts are only available as commercial. pad y pa d v ddp 0 v 50% y gnd v dd 50% t inyh 50% 50% in yl ibx t
proasic plus flash family fpgas 1-50 v5.8 table 1-37 ? worst-case military conditions v ddp = 3.0v, v dd = 2.3v, t j = 125c for military/mil-std-883 macro type description max. t inyh 1 max. t inyl 2 units std. std. ib33 3.3v, cmos input levels 3 , no pull-up resistor 0.5 0.6 ns ib33s 3.3v, cmos input levels 3 , no pull-up resistor, schmitt trigger 0.6 0.8 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. lvttl delays are the same as cmos delays. 4. for lp macros, v ddp =2.3v for delays. table 1-38 ? worst-case military conditions v ddp = 2.3v, v dd = 2.3v, t j = 125c for military/mil-std-883 macro type description max. t inyh 1 max. t inyl 2 units std. std. ib25lp 2.5v, cmos input levels 3 , low power 0.9 0.7 ns ib25lps 2.5v, cmos input levels 3 , low power, schmitt trigger 0.8 1.0 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. lvttl delays are the same as cmos delays. 4. for lp macros, v ddp =2.3v for delays.
proasic plus flash family fpgas v5.8 1-51 global input buffer delays table 1-39 ? worst-case commercial conditions v ddp = 3.0 v, v dd = 2.3 v, t j = 70c macro type description max. t inyh 1 max. t inyl 2 units std. 3 ?f std. 3 ?f gl33 3.3 v, cmos input levels 4 , no pull-up resistor 1.0 1.2 1.1 1.3 ns gl33s 3.3 v, cmos input levels 4 , no pull-up resistor, schmitt trigger 1.0 1.2 1.1 1.3 ns pecl ppecl input levels 1.0 1.2 1.1 1.3 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. applies to military proasic plus devices. 4. lvttl delays are the same as cmos delays. 5. for lp macros, v ddp =2.3 v for delays. 6. all ?f parts are only available as commercial. table 1-40 ? worst-case commercial conditions v ddp = 2.3 v, v dd = 2.3 v, t j = 70c macro type description max. t inyh 1 max. t inyl 2 units std. 3 ?f std. 3 ?f gl25lp 2.5 v, cmos input levels 4 , low power 1.1 1.2 1.0 1.3 ns gl25lps 2.5 v, cmos input levels 4 , low power, schmitt trigger 1.3 1.6 1.0 1.1 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. applies to military proasic plus devices. 4. lvttl delays are the same as cmos delays. 5. for lp macros, v ddp =2.3 v for delays. 6. all ?f parts are only available as commercial.
proasic plus flash family fpgas 1-52 v5.8 table 1-41 ? worst-case military conditions v ddp = 3.0v, v dd = 2.3v, t j = 125c for military/mil-std-883 macro type description max. t inyh 1 max. t inyl 2 std. std. gl33 3.3v, cmos input levels 3 , no pull-up resistor 1.1 1.1 gl33s 3.3v, cmos input levels 3 , no pull-up resistor, schmitt trigger 1.1 1.1 pecl ppecl input levels 1.1 1.1 notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. lvttl delays are the same as cmos delays. 4. for lp macros, v ddp =2.3v for delays. table 1-42 ? worst-case military conditions v ddp = 2.3v, v dd = 2.3v, t j = 125c for military/mil-std-883 macro type description max. t inyh 1 max. t inyl 2 std. std. gl25lp 2.5v, cmos input levels 3 , low power 1.0 1.1 gl25lps 2.5v, cmos input levels 3 , low power, schmitt trigger 1.4 1.0 notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low 3. lvttl delays are the same as cmos delays. 4. for lp macros, v ddp =2.3v for delays.
proasic plus flash family fpgas v5.8 1-53 predicted global routing delay global routing skew table 1-43 ? worst-case commercial conditions 1 v ddp = 3.0 v, v dd = 2.3 v, t j = 70c parameter description max. units std. ?f 2 t rckh input low to high 3 1.1 1.3 ns t rckl input high to low 3 1.0 1.2 ns t rckh input low to high 4 0.8 1.0 ns t rckl input high to low 4 0.8 1.0 ns notes: 1. the timing delay difference between tile locations is less than 15ps. 2. all ?f parts are only available as commercial. 3. highly loaded row 50%. 4. minimally loaded row. table 1-44 ? worst-case military conditions v ddp = 3.0v, v dd = 2.3v, t j = 125c for military/mil-std-883 parameter description max. units t rckh input low to high (high loaded row of 50%) 1.1 ns t rckl input high to low (high loaded row of 50%) 1.0 ns t rckh input low to high (minimally loaded row) 0.8 ns t rckl input high to low (minimally loaded row) 0.8 ns note: * the timing delay difference between tile locations is less than 15 ps. table 1-45 ? worst-case commercial conditions v ddp = 3.0 v, v dd = 2.3 v, t j = 70c parameter description max. units std. ?f* t rckswh maximum skew low to high 270 320 ps t rckshh maximum skew high to low 270 320 ps note: *all ?f parts are only available as commercial. table 1-46 ? worst-case commercial conditions v ddp = 3.0v, v dd = 2.3v, t j = 125c for military/mil-std-883 parameter description max. units t rckswh maximum skew low to high 270 ps t rckshh maximum skew high to low 270 ps
proasic plus flash family fpgas 1-54 v5.8 module delays sample macrocell library listing figure 1-29 ? module delays table 1-47 ? worst-case military conditions 1 v dd = 2.3 v, t j = 70o c, t j = 70c, t j = 125c for military/mil-std-883 cell name description std. ?f 2 max min max min units nand2 2-input nand 0.5 0.6 ns and2 2-input and 0.7 0.8 ns nor3 3-input nor 0.8 1.0 ns mux2l 2-1 mux with active low select 0.5 0.6 ns oa21 2-input or into a 2-input and 0.8 1.0 ns xor2 2-input exclusive or 0.6 0.8 ns ldl active low latch (lh/hl) lh 3 0.9 1.1 ns clk-q hl 3 0.8 0.9 ns t setup 0.7 0.8 ns t hold 0.1 0.2 ns dffl negative edge-triggered d-type flip-flop (lh/hl) clk-q lh 3 0.9 1.1 ns hl 3 0.8 1.0 ns t setup 0.6 0.7 ns t hold 0.0 0.0 ns notes: 1. intrinsic delays have a variable component, coupled to the input slope of the signal. these numbers assume an input slope typ ical of local interconnect. 2. all ?f parts are only available as commercial. 3. lh and hl refer to the q transitions from low to high and high to low, respectively. a b 50% y 50% 50% 50% 50% 50% dalh c 50%50% 50% 50% 50% dblh dahl dbhl dchl dclh 50% t t t t t t a b c y
proasic plus flash family fpgas v5.8 1-55 table 1-48 ? recommended operating conditions parameter symbol limits commercial/industrial military/mil-std-883 maximum clock frequency* f clock 180 mhz 180 mhz maximum ram frequency* f ram 150 mhz 150 mhz maximum rise/fall time on inputs* ? schmitt trigger mode (10% to 90%) ? non-schmitt trigger mode (10% to 90%) t r /t f t r /t f n/a 100 ns 100 ns 10 ns maximum lvpecl frequency* 180 mhz 180 mhz maximum tck frequency (jtag) f tck 10 mhz 10 mhz note: *all ?f parts will be 20% slower than standard commercial devices. table 1-49 ? slew rates measured at c = 30pf , nominal power supplies and 25c type trig. level rising edge (ns) slew rate (v/n s) falling edge (ns) slew rate (v/ns) pci mode ob33ph 10%-90% 1.60 1.65 1.65 1.60 yes ob33pn 10%-90% 1.57 1.68 3.32 0.80 no ob33pl 10%-90% 1.57 1.68 1.99 1.32 no ob33lh 10%-90% 3.80 0.70 4.84 0.55 no ob33ln 10%-90% 4.19 0.63 3.37 0.78 no ob33ll 10%-90% 5.49 0.48 2.98 0.89 no ob25lphh 10%-90% 1.55 1.29 1.56 1.28 no ob25lphn 10%-90% 1.70 1.18 2.08 0.96 no ob25lphl 10%-90% 1.97 1.02 2.09 0.96 no ob25lplh 10%-90% 3.57 0.56 3.93 0.51 no ob25lpln 10%-90% 4.65 0.43 3.28 0.61 no ob25lpll 10%-90% 5.52 0.36 3.44 0.58 no notes: 1. standard and ?f parts. 2. all ?f only available as commercial.
proasic plus flash family fpgas 1-56 v5.8 table 1-50 ? jtag switching characteristics description symbol min max unit output delay from tck falling to tdi, tms t tcktdi ?4 4 ns tdo setup time before tck rising t tdotck 10 ns tdo hold time after tck rising t tcktdo 0 ns tck period t tck 100 2 1,000 ns rck period t rck 100 1,000 ns notes: 1. for dc electrical specificati ons of the jtag pins (tck, td i, tms, tdo, trst), refer to table 1-22 on page 1-37 when v ddp = 2.5 v and table 1-24 on page 1-41 when v ddp = 3.3 v. 2. if rck is being used, there is no minimum on the tck period. figure 1-30 ? jtag operation timing tck tms, tdi tdo t tck t tcktdi t tcktdo t tdotck
proasic plus flash family fpgas v5.8 1-57 embedded memory specifications this section discusses proasic plus sram/fifo embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks ( table 1-51 ). table 1-13 on page 1-24 shows basic sram and fifo configurations. simu ltaneous read and write to the same location must be done with care. on such accesses the di bus is output to the do bus. refer to the proasic plus ram and fifo blocks application note for more information. enclosed timing diagrams?sram mode: ? "synchronous sram read, access timed output strobe (synchronous tr ansparent)" section on page 1-58 ? "synchronous sram read, pipeline mode outputs (synchronous pipelined)" section on page 1-59 ? "asynchronous sram write" section on page 1-60 ? "asynchronous sram read, address controlled, rdb=0" section on page 1-61 ? "asynchronous sram read, rdb controlled" section on page 1-62 ? "synchronous sram write" ? embedded memory specifications the difference between sy nchronous transparent and pipeline modes is the timing of all the output signals from the memory. in transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. if clock cycles are short (h igh clock speed), the data requires most of the clock cycle to change to valid values (stable signals). processing of this data in the same clock cycle is nearly impossible. mo st designers add registers at all outputs of the memory to push the data processing into the next clock cycle. an entire clock cycle can then be used to process the data. to simplify use of this memory setup, suitable registers have been implemented as part of th e memory primitive and are available to the user in the synchronous pipeline mode. in this mode, the output sign als will change shortly after the second rising edge, following the initiation of the read access. table 1-51 ? memory block sram interface signals sram signal bits in/out description wclks 1 in write clock used on synchronization on write side rclks 1 in read clock used on synchronization on read side raddr<0:7> 8 in read address rblkb 1 in true read block select (active low) rdb 1 in true read pulse (active low) waddr<0:7> 8 in write address wblkb 1 in write block select (active low) di<0:8> 9 in input data bits <0:8>, <8> can be used for parity in wrb 1 in negative true write pulse do<0:8> 9 out output data bits <0:8>, <8> can be used for parity out rpe 1 out read parity error (active high) wpe 1 out write parity error (active high) parodd 1 in selects odd parity generation/detect when high, even when low note: not all signals shown are used in all modes.
proasic plus flash family fpgas 1-58 v5.8 synchronous sram read, acce ss timed output strobe ( synchronous transparent) note: the plot shows the normal operation status. figure 1-31 ? synchronous sram read, access timed ou tput strobe (synchronous transparent) table 1-52 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns oca new do access from rclks 7.5 ns och old do valid from rclks 3.0 ns rach raddr hold from rclks 0.5 ns racs raddr setup to rclks 1.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 9.5 ns rpch old rpe valid from rclks 3.0 ns note: all ?f speed grade devices are 20% slower than the standard numbers. raddr rpe do rclks rbd, rblkb new valid data out cycle start old data out new valid address t racs t rdcs t rdch t rach t och t rpch t cmh t oca t rpca t ccyc t cml
proasic plus flash family fpgas v5.8 1-59 synchronous sram read, pipeline mode outputs (synchronous pipelined) note: the plot shows the normal operation status. figure 1-32 ? synchronous sram read, pipeline mode outputs (synchronous pipelined) table 1-53 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = 0c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns oca new do access from rclks 2.0 ns och old do valid from rclks 0.75 ns rach raddr hold from rclks 0.5 ns racs raddr setup to rclks 1.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 4.0 ns rpch old rpe valid from rclks 1.0 ns note: all ?f speed grade devices are 20% slower than the standard numbers. rclks rpe do new valid data out cycle start new rpe out raddr new valid address rdb, rblkb t racs t oca t rpch t och t rpca t cml t cmh t ccyc t rach t rdch t rdcs old data out old rpe out
proasic plus flash family fpgas 1-60 v5.8 asynchronous sram write note: the plot shows the normal operation status. figure 1-33 ? asynchronous sram write table 1-54 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883b symbol t xxx description min. max. units notes awrh waddr hold from wb 1.0 ns awrs waddr setup to wb 0.5 ns dwrh di hold from wb 1.5 ns dwrs di setup to wb 0.5 ns pargen is inactive. dwrs di setup to wb 2.5 ns pargen is active. wpda wpe access from di 3.0 ns w pe is invalid, while pargen is active. wpdh wpe hold from di 1.0 ns wrcyc cycle time 7.5 ns wrmh wb high phase 3.0 ns inactive wrml wb low phase 3.0 ns active note: all ?f speed grade devices are 20% slower than the standard numbers. wrb, wblkb waddr wpe di t awrs t wpda t awrh t dwrs t wrml t wrmh t wrcyc t wpdh t dwrh
proasic plus flash family fpgas v5.8 1-61 asynchronous sram read, a ddress controlled, rdb=0 note: the plot shows the normal operation status. figure 1-34 ? asynchronous sram read, address controlled, rdb=0 table 1-55 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883b symbol t xxx description min. max. units notes acyc read cycle time 7.5 ns oaa new do access from raddr stable 7.5 ns oah old do hold from raddr stable 3.0 ns rpaa new rpe access from raddr stable 10.0 ns rpah old rpe hold from raddr stable 3.0 ns note: all ?f speed grade devices are 20% slower than the standard numbers. rpe do raddr t oah t rpah t oaa t rpaa t acyc
proasic plus flash family fpgas 1-62 v5.8 asynchronous sram read, rdb controlled note: the plot shows the normal operation status. figure 1-35 ? asynchronous sram read, rdb controlled table 1-56 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns rdcyc read cycle time 7.5 ns rdmh rb high phase 3.0 ns inactive setup to new cycle rdml rb low phase 3.0 ns active rprda new rpe access from rb 9.5 ns rprdh old rpe valid from rb 3.0 ns note: all ?f speed grade devices are 20% slower than the standard numbers. rb=(rdb+rblkb) rpe do t ordh t orda t rprda t rdml t rdcyc t rdmh t rprdh
proasic plus flash family fpgas v5.8 1-63 synchronous sram write note: the plot shows the normal operation status. figure 1-36 ? synchronous sram write table 1-57 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns dch di hold from wclks 0.5 ns dcs di setup to wclks 1.0 ns wach waddr hold from wclks 0.5 ns wdcs waddr setup to wclks 1.0 ns wpca new wpe access from wclks 3.0 ns wpe is invalid while pargen is active wpch old wpe valid from wclks 0.5 ns wrch, wbch wrb & wblkb hold from wclks 0.5 ns wrcs, wbcs wrb & wblkb setup to wclks 1.0 ns notes: 1. on simultaneous read and write accesses to the same location, di is output to do. 2. all ?f speed grade devices are 20% slower than the standard numbers. wclks wpe waddr, di wrb, wblkb cycle start t wrch , t wbch t wrcs , t wbcs t dcs , t wdcs t wpch t dch , t wach t wpca t cmh t cml t ccyc
proasic plus flash family fpgas 1-64 v5.8 synchronous write and read to the same location note: the plot shows the normal operation status. figure 1-37 ? synchronous write and read to the same location table 1-58 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns wclkrclks wclks to rclks setup time ? 0.1 ns wclkrclkh wclks to rclks hold time 7.0 ns och old do valid from rclks 3.0 ns oca/och displayed for access timed output oca new do valid from rclks 7.5 ns notes: 1. this behavior is valid for access timed output and pipelined mode output. the table shows the timings of an access timed outp ut. 2. during synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same ti me as the active read clock edge. the negati ve setup time insures this behavior for w clks and rclks driven by the same design signal. 3. if wclks changes after the hold time, the data will be read. 4. a setup or hold time violation will result in unknown output data. 5. all ?f speed grade devices are 20% slower than the standard numbers. * new data is read if wclks occurs before setup time. the data stored is read if wclks occurs after hold time. rclks do wclks t wclkrclkh new data* last cycle data t wclkrclks t och t ccyc t cmh t cml t oca
proasic plus flash family fpgas v5.8 1-65 asynchronous write and synchronou s read to the same location note: the plot shows the normal operation status. figure 1-38 ? asynchronous write and synchrono us read to the same location table 1-59 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns wbrclks wb to rclks setup time ? 0.1 ns wbrclkh wb to rclks hold time 7.0 ns och old do valid from rclks 3.0 ns oca/och displayed for access timed output oca new do valid from rclks 7.5 ns dwrrclks di to rclks setup time 0 ns dwrh di to wb hold time 1.5 ns notes: 1. this behavior is valid for access timed output and pipelined mode output. the table shows the timings of an access timed outp ut. 2. in asynchronous write and synchronous read access to the same lo cation, the new write data will be read out if the active wri te signal edge occurs before or at the same time as the active read clock edge. if wb changes to low after hold time, the data wil l be read. 3. a setup or hold time violation will result in unknown output data. 4. all ?f speed grade devices are 20% slower than the standard numbers. * new data is read if wb occurs before setup time. the stored data is read if wb occurs after hold time. wb = {wrb + wblkb} rclks do t brclkh new data* last cycle data t wrcks t och t oca di t dwrrclks t dwrh t ccyc t cmh t cml
proasic plus flash family fpgas 1-66 v5.8 asynchronous write and read to the same location note: the plot shows the normal operation status. figure 1-39 ? asynchronous write and read to the same location table 1-60 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v fo r commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns owra new do access from wb 3.0 ns owrh old do valid from wb 0.5 ns rawrs rb or raddr from wb 5.0 ns rawrh rb or raddr from wb 5.0 ns notes: 1. during an asynchronous read cycle, each write operation (synch ronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. refer to the proasic plus ram and fifo blocks application note for more information. 2. violation or rawrs will disturb access to the old data. 3. violation of rawrh will disturb access to the newer data. 4. all ?f speed grade devices are 20% slower than the standard numbers. rb, raddr old newer new t orda t ordh t owrh t rawrh wb = {wrb+wblkb} do t owra t rawrs
proasic plus flash family fpgas v5.8 1-67 synchronous write and asynchronou s read to the same location note: the plot shows the normal operation status. figure 1-40 ? synchronous write and asynchrono us read to the same location table 1-61 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns owra new do access from wclks 3.0 ns owrh old do valid from wclks 0.5 ns rawclks rb or raddr from wclks 5.0 ns rawclkh rb or raddr from wclks 5.0 ns notes: 1. during an asynchronous read cycle, each write operation (synch ronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. violation of rawclks will disturb access to old data. 3. violation of rawclkh will disturb access to newer data. 4. all ?f speed grade devices are 20% slower than the standard numbers. rb, raddr old new newer t orda t ordh t rawclks t rawclkh wclks do t owrh t owra
proasic plus flash family fpgas 1-68 v5.8 asynchronous fifo full and empty transitions the asynchronous fifo acce pts writes and reads while not full or not empty. when th e fifo is full, all writes are inhibited. conversely, when th e fifo is empty, all reads are inhibited. a problem is cr eated if the fifo is written to during the transition fr om full to not full, or read during the transition from empty to not empty. the exact time at which the writ e or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. for slow cycles, this indeterminate period starts 1 ns after the rb (wb) transition, which deactivates full or not empty and ends 3 ns after the rb (wb) transition. for fast cycles, the indeterminate period ends 3 ns (7.5 ns ? rdl (wrl)) after the rb (wb) transition, whichever is later ( table 1-1 on page 1-7 ). the timing diagram for write is shown in figure 1-38 on page 1-65 . the timing diagram for read is shown in figure 1-39 on page 1-66 . for basic sram configurations, see table 1-14 on page 1-25 . when reset is asserted, the empty flag will be asserted, the counters will reset, the outputs go to zero, but the internal ram is not erased. enclosed timing diagr ams ? fifo mode: the following timing diagrams apply only to single cell; they are not applicable to cascaded cells. for more information, refer to the proasic plus ram/fifo blocks application note. ? "asynchronous fifo read" section on page 1-70 ? "asynchronous fifo write" section on page 1-71 ? "synchronous fifo read, access timed output strobe (synchronous tr ansparent)" section on page 1-72 ? "synchronous fifo read, pipeline mode outputs (synchronous pipelined)" section on page 1-73 ? "synchronous fifo write" section on page 1-74 ? "fifo reset" section on page 1-75 table 1-62 ? memory block fifo interface signals fifo signal bits in/out description wclks 1 in write clock used for synchronization on write side rclks 1 in read clock used for synchronization on read side level <0:7>* 8 in direct configuratio n implements static flag logic rblkb 1 in read block select (active low) rdb 1 in read pulse (active low) reset 1 in reset for fifo pointers (active low) wblkb 1 in write block select (active low) di<0:8> 9 in input data bits <0:8>, <8> will be generated if pargen is true wrb 1 in write pulse (active low) full, empty 2 out fifo flags. full prev ents write and empty prevents read eqth, geqth* 2 out eqth is true when the fifo holds the number of words specified by the level signal. geqth is true when the fifo holds (level) words or more do<0:8> 9 out output data bits <0:8> rpe 1 out read parity error (active high) wpe 1 out write parity error (active high) lgdep <0:2> 3 in configures depth of the fifo to 2 (lgdep+1) parodd 1 in selects odd parity generation/detect when high, even when low note: *level is always eight bits (0000.0000, 0000.0001). that means fo r values of depth greater than 256, not all values will be possible, e.g. for depth=512, the level can onl y have the values 2, 4, . . ., 512. th e level signal circuit will generate signa ls that indicate whether the fifo is exactly filled to the value of level (eqth) or filled eq ual or higher (geqth) than the specified l evel. since counting starts at 0, eqth wi ll become true when the fifo holds (level+1) words for 512-bit fifos.
proasic plus flash family fpgas v5.8 1-69 note: all ?f speed grade devices are 20% slower than the standard numbers. figure 1-41 ? write timing diagram note: all ?f speed grade devices are 20% slower than the standard numbers. figure 1-42 ? read timing diagram write accepted write inhibited full rb write cycle 1 ns 3 ns wb read accepted read inhibited empty wb read cycle 1 ns 3 ns rb
proasic plus flash family fpgas 1-70 v5.8 asynchronous fifo read note: the plot shows the normal operation status. figure 1-43 ? asynchronous fifo read table 1-63 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes erdh, frdh, thrdh old empty, full, eqth, & geth valid hold time from rb 0.5 ns empty/full/thresh are invalid from the end of hold until the new access is complete erda new empty access from rb 3.0 1 ns frda full access from rb 3.0 1 ns orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns rdcyc read cycle time 7.5 ns rdwrs wb , clearing empty, setup to rb 3.0 2 ns enabling the read operation 1.0 ns inhibiting the read operation rdh rb high phase 3.0 ns inactive rdl rb low phase 3.0 ns active rprda new rpe access from rb 9.5 ns rprdh old rpe valid from rb 4.0 ns thrda eqth or geth access from rb 4.5 ns notes: 1. at fast cycles, erda and frda = max (7.5 ns ? rdl), 3.0 ns. 2. at fast cycles, rdwrs (for enabli ng read) = max (7.5 ns ? wrl), 3.0 ns. 3. all ?f speed grade devices are 20% slower than the standard numbers. rb = (rdb+rblkb) rpe rdata empty eqth, geth full (empty inhibits read) cycle start wb t rdwrs t erdh , t frdh t erda , t frda t thrdh t ordh t rprdh t orda t rprda t rdl t rdh t rprda t rdl t rdcyc t rdh t thrda
proasic plus flash family fpgas v5.8 1-71 asynchronous fifo write note: the plot shows the normal operation status. figure 1-44 ? asynchronous fifo write table 1-64 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes dwrh di hold from wb 1.5 ns dwrs di setup to wb 0.5 ns pargen is inactive dwrs di setup to wb 2.5 ns pargen is active ewrh, fwrh, thwrh old empty, full, eqth, & geth valid hold time after wb 0.5 ns empty/full/thresh are invalid from the end of hold until the new access is complete ewra empty access from wb 3.0 1 ns fwra new full access from wb 3.0 1 ns thwra eqth or geth access from wb 4.5 ns wpda wpe access from di 3.0 ns wpe is invalid while pargen is active wpdh wpe hold from di 1.0 ns wrcyc cycle time 7.5 ns wrrds rb , clearing full, setup to wb 3.0 2 ns enabling the write operation 1.0 inhibiting the write operation wrh wb high phase 3.0 ns inactive wrl wb low phase 3.0 ns active notes: 1. at fast cycles, ewra, fwra = max (7.5 ns ? wrl), 3.0 ns. 2. at fast cycles, wrrds (for enabling write) = max (7.5 ns ? rdl), 3.0 ns. 3. all ?f speed grade devices are 20% slower than the standard numbers. 4. after fifo reset, wrb needs an initial falling edge prior to any write actions. wpe wdata (full inhibits write) wb = (wrb+wblkb) empty eqth, geth full cycle start rb t wrrds t dwrh t wpdh t wpda t dwrs t ewrh , t fwrh t ewra , t fwra t thwrh t thwra t wrh t wrl t wrcyc
proasic plus flash family fpgas 1-72 v5.8 synchronous fifo read, acce ss timed output strobe (synchronous transparent) note: the plot shows the normal operation status. figure 1-45 ? synchronous fifo read, access timed ou tput strobe (synchronous transparent) table 1-65 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns ecba new empty access from rclks 3.0 1 ns fcba full access from rclks 3.0 1 ns ecbh, fcbh, thcbh old empty, full, eqth, & geth valid hold time from rclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete oca new do access from rclks 7.5 ns och old do valid from rclks 3.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 9.5 ns rpch old rpe valid from rclks 3.0 ns hcba eqth or geth access from rclks 4.5 ns notes: 1. at fast cycles, ecba and fc ba = max (7.5 ns ? cmh), 3.0 ns. 2. all ?f speed grade devices are 20% slower than the standard numbers. rclk rpe rdata empty eqth, geth full rdb t rdch t och t rpch t rdcs old data out new valid data out (empty inhibits read) cycle start t ecbh , t fcbh t ecba , t fcba t oca t rpca t cmh t cml t ccyc t thcbh t hcba
proasic plus flash family fpgas v5.8 1-73 synchronous fifo read, pi peline mode outputs (s ynchronous pipelined) note: the plot shows the normal operation status. figure 1-46 ? synchronous fifo read, pipeline mode outputs (synchronous pipelined) table 1-66 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns ecba new empty access from rclks 3.0 1 ns fcba full access from rclks 3.0 1 ns ecbh, fcbh, thcbh old empty, full, eqth, & geth valid hold time from rclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete oca new do access from rclks 2.0 ns och old do valid from rclks 0.75 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 4.0 ns rpch old rpe valid from rclks 1.0 ns hcba eqth or geth access from rclks 4.5 ns notes: 1. at fast cycles, ecba and fc ba = max (7.5 ns ? cms), 3.0 ns. 2. all ?f speed grade devices are 20% slower than the standard numbers. rclk rpe rdata empty eqth, geth full old data out new valid data out rdb cycle start old rpe out new rpe out t ecbh , t fcbh t rdch t rdcs t oca t ecba , t fcba t thcbh t hcba t cmh t cml t ccyc t rpch t och t rpca
proasic plus flash family fpgas 1-74 v5.8 synchronous fifo write note: the plot shows the normal operation status. figure 1-47 ? synchronous fifo write table 1-67 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns dch di hold from wclks 0.5 ns dcs di setup to wclks 1.0 ns fcba new full access from wclks 3.0 1 ns ecba empty access from wclks 3.0 1 ns ecbh, fcbh, hcbh old empty, full, eqth, & geth valid hold time from wclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete hcba eqth or geth access from wclks 4.5 ns wpca new wpe access from wclks 3.0 ns wpe is invalid, while pargen is active wpch old wpe valid from wclks 0.5 ns wrch, wbch wrb & wblkb hold from wclks 0.5 ns wrcs, wbcs wrb & wblkb setup to wclks 1.0 ns notes: 1. at fast cycles, ecba and fc ba = max (7.5 ns ? cmh), 3.0 ns. 2. all ?f speed grade devices are 20% slower than the standard numbers. wclks wpe di empty eqth, geth full (full inhibits write) wrb, wblkb cycle start t wrch , t wbch t ecbh , t fcbh t ecba , t fcba t hcba t wrcs , t wbcs t dcs t wpca t cmh t cml t ccyc t wpch t dch t hcbh
proasic plus flash family fpgas v5.8 1-75 fifo reset notes: 1. during reset, either the enables (wrb and rbd) or the clocks (wclks and rckls) must be low. 2. the plot shows the normal operation status. figure 1-48 ? fifo reset table 1-68 ? t j = 0c to 110c; v dd = 2.3 v to 2.7 v for commercial/industrial t j = ?55c to 150c, v dd = 2.3 v to 2.7 v for military/mil-std-883 symbol t xxx description min. max. units notes cbrsh 1 wclks or rclks hold from resetb 1.5 ns synchronous mode only cbrss 1 wclks or rclks setup to resetb 1.5 ns synchronous mode only ersa new empty access from resetb 3.0 ns frsa full access from resetb 3.0 ns rsl resetb low phase 7.5 ns thrsa eqth or geth access from resetb 4.5 ns wbrsh 1 wb hold from resetb 1.5 ns asynchronous mode only wbrss 1 wb setup to resetb 1.5 ns asynchronous mode only notes: 1. during rest, the enables (wrb and rbd) must be hi gh or the clocks (wclks and rckls) must be low. 2. all ?f speed grade devices are 20% slower than the standard numbers. resetb empty eqth, geth full wrb/rbd 1 cycle start cycle start wclks, rclks 1 t ersa , t frsa t thrsa t cbrss t wbrss t cbrsh t wbrsh t rsl
pin description user pins i/o user input/output the i/o pin functions as an input, output, tristate, or bidirectional buffer. input and output signal levels are compatible with standard lvttl and lvcmos specifications. unused i/o pins are configured as inputs with pull-up resistors. nc no connect to maintain compatibility with other actel proasic plus products, it is recommended that this pin not be connected to the circuitry on the board. gl global pin low skew input pin for clock or other global signals. this pin can be configured with an internal pull-up resistor. when it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal i/o. glmx global multiplexing pin low skew input pin for clock or other global signals. this pin can be used in one of two special ways (refer to actel?s using proasic plus clock conditioning circuits ). when the external feedback option is selected for the pll block, this pin is rout ed as the external feedback source to the clock conditioning circuit. in applications where two di fferent signals access the same global net at different times through the use of glmxx and glmxlx macros, this pin will be fixed as one of the source pins. this pin can be configured with an internal pull-up resistor. when it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal i/o. if not used, the glmxx pin will be configured as an input with pull-up. dedicated pins gnd ground common ground supply voltage. v dd logic array power supply pin 2.5 v supply voltage. v ddp i/o pad power supply pin 2.5 v or 3.3 v supply voltage. tms test mode select the tms pin controls the use of boundary-scan circuitry. this pin has an internal pull-up resistor. tck test clock clock input pin for boundary sc an (maximum 10 mhz). actel recommends adding a nominal 20 k pull-up resistor to this pin. tdi test data in serial input for boundary scan. a dedicated pull-up resistor is included to pull this pin high when not being driven. tdo test data out serial output for boundary scan. actel recommends adding a nominal 20k pull-up resistor to this pin. trst test reset input asynchronous, active-low input pin for resetting boundary-scan circuitry. this pin has an internal pull-up resistor. for more information, please refer to power-up behavior of proasic plus devices application note. special function pins rck running clock a free running clock is needed during programming if the programmer cannot guarantee that tck will be uninterrupted. if not used, th is pin has an internal pull- up and can be left floating. npecl user negative input provides high speed clock or data signals to the pll block. if unused, leave the pin unconnected. ppecl user positive input provides high speed clock or data signals to the pll block. if unused, leave the pin unconnected. avdd pll power supply analog v dd should be v dd (core voltage) 2.5 v (nominal) and be decoupled from gnd with suitable decoupling capacitors to reduce noise. for more information, refer to actel?s using proasic plus clock conditioning circuits application note. if the clock conditioning circuitry is not used in a design, avdd can either be left floating or tied to 2.5 v. agnd pll power ground the analog ground can be connected to the system ground. for more information, refer to actel?s using proasic plus clock conditioning circuits application note. if the plls or clock conditioning circuitry are not used in a design, agnd should be tied to gnd.
proasic plus flash family fpgas v5.8 1-77 v pp programming supply pin this pin may be connected to any voltage between gnd and 16.5 v during normal operation, or it can be left unconnected. 2 for information on using this pin during programming, see the in-system programming proasic plus devices application note. actel recommends floating the pin or connecting it to v ddp . v pn programming supply pin this pin may be connected to any voltage between 0.5v and ?13.8 v during normal operation, or it can be left unconnected. 3 for information on using this pin during programming, see the in-system programming proasic plus devices application note. actel recommends floating the pin or connecting it to gnd. recommended design practice for v pn /v pp proasic plus devices ? apa450, apa600, apa750, apa1000 bypass capacitors are required from v pp to gnd and v pn to gnd for all proasic plus devices during programming. during the erase cycle, proasic plus devices may have current surges on the v pp and v pn power supplies. the only way to maintain the integrity of the power distribution to the proasic plus device during these current surges is to counteract the inductance of the finite length conductors that distribute the power to the device. this can be accomplished by providing sufficient bypass capacitance between the v pp and v pn pins and gnd (using the shortest paths possible). without sufficient bypass capacitance to counteract the inductance, the v pp and v pn pins may incur a voltage spike beyond the voltage that the device can withstand. this issue applies to all programming configurations. the solution prevents spikes from damaging the proasic plus devices. bypass capacitors are required for the v pp and v pn pads. use a 0.01 f to 0.1 f ceramic capacitor with a 25 v or greater rating. to filter low- frequency noise (decoupling), use a 4.7 f (low esr, <1 < , tantalum, 25 v or greater rating) capacitor. the capacitors should be located as close to the device pins as possible (within 2.5 cm is desirable). the smaller, high- frequency capacitor should be placed closer to the device pins than the larger low-fr equency capacitor. the same dual-capacitor circuit should be used on both the v pp and v pn pins ( figure 1-49 ). proasic plus devices ? apa075, apa150, apa300 these devices do not require bypass capacitors on the v pp and v pn pins as long as the total combined distance of the programming cable and the trace length on the board is less than or equal to 30 inches. note: for trace lengths greater than 30 inches, use the bypass capacitor recommendations in the previous section. 2. there is a nominal 40 k pull-up resistor on v pp . 3. there is a nominal 40 k pull-down resistor on v pn . figure 1-49 ? proasic plus v pp and v pn capacitor requirements 2.5cm 0.1 f to 0.01 f programming header or supplies 4.7 f actel proasic device + + + _ v pp v pn + _ 0.1 f to 0.01 f 4.7 f plus

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